XC5VLX50T-1FF665C Xilinx Inc, XC5VLX50T-1FF665C Datasheet - Page 187

• Manufacturer Part Number: XC5VLX50T-1FF665C
• Description: FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FF665C

• Package: 665FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 46080
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 360
• Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
X-Ref Target - Figure 5-12
If two single-port 128 x 1-bit modules are built, the two RAM128X1S primitives can occupy
a SLICEM, as long as they share the same clock, write enable, and shared read and write
port address inputs. This configuration equates to 128 x 2-bit single-port distributed RAM.
WCLK
A[6:0]
WE
D
A6 (CX)
Figure 5-12: Distributed RAM (RAM128X1S)
(WE/CE)
www.xilinx.com
(CLK)
(DX)
[5:0]
[5:0]
RAM128X1S
7
7
DI1
A[6:1]
WA[7:1]
CLK
WE
DI1
A[6:1]
WA[7:1]
CLK
WE
SPRAM64
SPRAM64
O6
O6
F7BMUX
0
D Q
(Optional)
ug190_5_12_050506
CLB Overview
Output
Registered
Output
187