XC5VLX50T-1FF665C Xilinx Inc, XC5VLX50T-1FF665C Datasheet - Page 233

• Manufacturer Part Number: XC5VLX50T-1FF665C
• Description: FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXTr

Specifications of XC5VLX50T-1FF665C

• Package: 665FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 46080
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 360
• Ram Bits: 2211840
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Total Ram Bits: 2211840
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex-5 FPGA SelectIO Primitives
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
IBUF and IBUFG
OBUF
The Xilinx software library includes an extensive list of primitives to support a variety of
I/O standards available in the Virtex-5 FPGA I/O primitives. The following are five
generic primitive names representing most of the available single-ended I/O standards.
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These six generic primitive names represent most of the available differential I/O
standards:
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Signals used as inputs to Virtex-5 devices must use an input buffer (IBUF). The generic
Virtex-5 FPGA IBUF primitive is shown in
X-Ref Target - Figure 6-18
The IBUF and IBUFG primitives are the same. IBUFGs are used when an input buffer is
used as a clock input. In the Xilinx software tools, an IBUFG is automatically placed at
clock input sites.
An output buffer (OBUF) must be used to drive signals from Virtex-5 devices to external
output pads. A generic Virtex-5 FPGA OBUF primitive is shown in
X-Ref Target - Figure 6-19
IBUF (input buffer)
IBUFG (clock input buffer)
OBUF (output buffer)
OBUFT (3-state output buffer)
IOBUF (input/output buffer)
IBUFDS (input buffer)
IBUFGDS (clock input buffer)
OBUFDS (output buffer)
OBUFTDS (3-state output buffer)
IOBUFDS (input/output buffer)
IBUFDS_DIFF_OUT (input buffer)
Figure 6-18: Input Buffer (IBUF/IBUFG) Primitives
Figure 6-19: Output Buffer (OBUF) Primitive
From device pad
From FPGA
I (Input)
www.xilinx.com
I (Input)
OBUF
IBUF/IBUFG
Figure
6-18.
Virtex-5 FPGA SelectIO Primitives
ug190_6_17_022806
O (Output)
to device pad
ug190_6_16_022806
O (Output)
into FPGA
Figure
6-19.
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