TXC-06412BIOG Transwitch Corporation, TXC-06412BIOG Datasheet - Page 204

• Manufacturer Part Number: TXC-06412BIOG
• Manufacturer: Transwitch Corporation

Specifications of TXC-06412BIOG

• Lead Free Status / RoHS Status: Not Compliant

PHAST-12P Device
DATA SHEET
TXC-06412B
PRELIMINARY TXC-06412B-MB, Ed. 2
June 2005
0x0002
0x0004
0x0006
0x0000
0x0002
0x0004
Offset
Offset
4 - 0
4 - 0
5 - 0
4 - 0
4 - 0
0
Bits
Bits
SysLoop
FacLoop
IndirectAccessMode
RxPAD
TxPAD
TxRefClock2
Table 67: High Speed Interface Power Down
Table 66: CDR/CS Configuration
Name
Name
-
Memory Maps and Bit Descriptions
Init
Init
0x1F
0x1F
0x0
0x0
0x0
0x1
System Loopback Select, it routes the serialized transmit output
to the deserializer receive input.
Each bit controls a line. The corresponding LIU is in normal oper-
ation when 0x0 and is looped back when 0x1.
•
•
•
•
•
Facility Loopback Select, it routes the receive serial input back to
the transmit serial output.
Each bit controls a line. The corresponding LIU is in normal oper-
ation when 0x0 and is looped back when 0x1.
•
•
•
•
•
Selects the mode for the IndirectAccessData register.
•
•
•
Power Down for the Receive Line and APS pads.
Each bit controls a receive pad. The corresponding pad is powered
down when 0x1.
•
•
•
•
•
Power Down for the Transmit Line and APS pads.
Each bit controls a transmit pad. The corresponding pad is powered
down when 0x1.
•
•
•
•
•
Power Down for the Transmit Reference Clock Pad, REFTXCLK2.
The pad is powered down when 0x1.
bit 0: Line 1
bit 1: Line 2
bit 2: Line 3
bit 3: Line 4
bit 4: APS
bit 0: Line 1
bit 1: Line 2
bit 2: Line 3
bit 3: Line 4
bit 4: APS
0x0: Mode0
0x8: Mode1
All others: Reserved
bit 0: Line 1
bit 1: Line 2
bit 2: Line 3
bit 3: Line 4
bit 4: APS
bit 0: Line 1
bit 1: Line 2
bit 2: Line 3
bit 3: Line 4
bit 4: APS
(T_ANALOG_Common_Config)
-
(T_PadPowerDown)
Description
Description
2 0 4 o f 2 26