PIC12F1822-E/SN Microchip Technology, PIC12F1822-E/SN Datasheet - Page 126

• Manufacturer Part Number: PIC12F1822-E/SN
• Description: 3.5 KB Flash, 128 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 S
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 12Fr

Specifications of PIC12F1822-E/SN

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC12F/LF1822/PIC16F/LF1823
REGISTER 12-6:
TABLE 12-2:
TABLE 12-3:
DS41413B-page 126
CONFIG1
Legend:
Note
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7-6
bit 5-0
Note 1:
ANSELA
APFCON
LATA
OPTION_REG
PORTA
TRISA
WPUA
Legend:
Note 1:
Name
Name
U-0
—
1:
2:
2:
— = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA.
PIC12F1822/16F1823 only.
Global WPUEN bit of the OPTION register must be cleared for individual pull-ups to be enabled.
The weak pull-up device is automatically disabled if the pin is in configured as an output.
x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
PIC12F1822/16F1823 only.
PIC16F/LF1823 only.
Bits
13:8
7:0
RXDTSEL
Unimplemented: Read as ‘0’
WPUA<5:0>: Weak Pull-up Register bits
1 = Pull-up enabled
0 = Pull-up disabled
WPUEN
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
SUMMARY OF CONFIGURATION WORD WITH PORTA
Bit 7
—
—
—
—
—
Bit -/7
U-0
CP
—
—
WPUA: WEAK PULL-UP PORTA REGISTER
SDOSEL
INTEDG
Bit 6
MCLRE
Bit -/6
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
—
—
—
—
—
—
R/W-1/1
WPUA5
TMR0CS
TRISA5
WPUA5
SSSEL
LATA5
Bit 5
Bit 13/5
FCMEN
PWRTE
RA5
—
R/W-1/1
WPUA4
Preliminary
TMR0SE
WPUA4
TRISA4
ANSA4
LATA4
Bit 4
RA4
Bit 12/4
—
IESO
WDTE<1:0>
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
R/W-1/1
WPUA3
T1GSEL
TRISA3
WPUA3
CLKOUTEN
Bit 3
PSA
RA3
Bit 11/3
—
—
TXCKSEL
TRISA2
WPUA2
ANSA2
LATA2
Bit 2
RA2
Bit 10/2
R/W-1/1
WPUA2
BOREN<1:0>
PS<2:0>
FOSC<2:0>
P1BSEL
TRISA1
WPUA1
ANSA1
LATA1
 2010 Microchip Technology Inc.
Bit 1
RA1
Bit 9/1
R/W-1/1
WPUA1
CCP1SEL
WPUA0
TRISA0
ANSA0
LATA0
Bit 0
RA0
Bit 8/0
CPD
R/W-1/1
WPUA0
Register
on Page
Register
on Page
125
121
125
175
124
124
126
50
bit 0