PIC12F1822-E/SN Microchip Technology, PIC12F1822-E/SN Datasheet - Page 78

• Manufacturer Part Number: PIC12F1822-E/SN
• Description: 3.5 KB Flash, 128 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 S
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 12Fr

Specifications of PIC12F1822-E/SN

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC12F/LF1822/PIC16F/LF1823
7.1
The POR circuit holds the device in Reset until V
reached an acceptable level for minimum operation.
Slow rising V
performance may require greater than minimum V
The PWRT, BOR or MCLR features can be used to
extend the start-up period until all device operation
conditions have been met.
7.1.1
The Power-up Timer provides a nominal 64 ms time-
out on POR or Brown-out Reset.
The device is held in Reset as long as PWRT is active.
The PWRT delay allows additional time for the V
rise to an acceptable level. The Power-up Timer is
enabled by clearing the PWRTE bit in Configuration
Word 1.
The Power-up Timer starts after the release of the POR
and BOR.
For additional information, refer to Application Note
AN607, “Power-up Trouble Shooting” (DS00607).
TABLE 7-1:
7.2.1
When the BOREN bits of Configuration Word 1 are set
to ‘11’, the BOR is always on. The device start-up will
be delayed until the BOR is ready and V
than the BOR threshold.
BOR protection is active during Sleep. The BOR does
not delay wake-up from Sleep.
7.2.2
When the BOREN bits of Configuration Word 1 are set
to ‘10’, the BOR is on, except in Sleep. The device
start-up will be delayed until the BOR is ready and V
is higher than the BOR threshold.
BOR protection is not active during Sleep. The device
wake-up will be delayed until the BOR is ready.
DS41413B-page 78
BOR_ON (11)
BOR_NSLEEP (10)
BOR_NSLEEP (10)
BOR_SBOREN (01)
BOR_SBOREN (01)
BOR_OFF (00)
Note 1: Even though this case specifically waits for the BOR, the BOR is already operating, so there is no delay in
Config bits
Power-on Reset (POR)
BOREN
POWER-UP TIMER (PWRT)
start-up.
BOR IS ALWAYS ON
BOR IS OFF IN SLEEP
DD
, fast operating speeds or analog
BOR OPERATING MODES
SBOREN
X
X
X
1
0
X
DD
is higher
DD
Device Mode
DD
Preliminary
has
DD
Awake
Sleep
DD
to
.
X
X
X
X
7.2
The BOR circuit holds the device in Reset when V
reaches a selectable minimum level. Between the
POR and BOR, complete voltage range coverage for
execution protection can be implemented.
The Brown-out Reset module has four operating
modes controlled by the BOREN<1:0> bits in Configu-
ration Word 1. The four operating modes are:
• BOR is always on
• BOR is off when in Sleep
• BOR is controlled by software
• BOR is always off
Refer to
The Brown-out Reset voltage level is selectable by
configuring the BORV bit in Configuration Word 2.
A V
gering on small events. If V
duration greater than parameter T
will reset. See
7.2.3
When the BOREN bits of Configuration Word 1 are set
to ‘01’, the BOR is controlled by the SBOREN bit of the
BORCON register. The device start-up is not delayed
by the BOR ready condition or the V
BOR protection begins as soon as the BOR circuit is
ready. The status of the BOR circuit is reflected in the
BORRDY bit of the BORCON register.
BOR protection is unchanged by Sleep.
DD
BOR Mode
Disabled
Disabled
Disabled
Active
Active
Active
noise rejection filter prevents the BOR from trig-
Table 7-1
Brown-Out Reset (BOR)
BOR CONTROLLED BY SOFTWARE
Figure 7-3
for more information.
Operation upon
release of POR
Device
 2010 Microchip Technology Inc.
Waits for BOR ready
for more information.
Waits for BOR ready
Begins immediately
Begins immediately
Begins immediately
DD
falls below V
BORDC
DD
Operation upon
wake- up from
level.
, the device
Device
Sleep
BOR
(1)
for a
DD