PIC12F1822-E/SN Microchip Technology, PIC12F1822-E/SN Datasheet - Page 95

• Manufacturer Part Number: PIC12F1822-E/SN
• Description: 3.5 KB Flash, 128 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 S
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 12Fr

Specifications of PIC12F1822-E/SN

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.5.5
The PIR2 register contains the interrupt flag bits, as
shown in
REGISTER 8-5:
 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
Note 1:
R/W-0/0
OSFIF
Register
PIC16F/LF1823 only.
PIR2 REGISTER
OSFIF: Oscillator Fail Interrupt Flag
1 = Interrupt is pending
0 = Interrupt is not pending
C2IF: Comparator C2 Interrupt Flag
1 = Interrupt is pending
0 = Interrupt is not pending
C1IF: Comparator C1 Interrupt Flag
1 = Interrupt is pending
0 = Interrupt is not pending
EEIF: EEPROM Write Completion Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
BCLIF: MSSP Bus Collision Interrupt Flag bit
1 = Interrupt is pending
0 = Interrupt is not pending
Unimplemented: Read as ‘0’
8-5.
R/W-0/0
C2IF
PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2
(1)
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
R/W-0/0
C1IF
PIC12F/LF1822/PIC16F/LF1823
R/W-0/0
EEIF
Preliminary
(1)
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
R/W-0/0
BCLIF
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE, of the INTCON register.
User
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
U-0
—
software
U-0
should
—
DS41413B-page 95
ensure
U-0
—
bit 0
the