PIC12F1840T-I/SN Microchip Technology, PIC12F1840T-I/SN Datasheet - Page 17

• Manufacturer Part Number: PIC12F1840T-I/SN
• Description: 7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 SOI
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 12Fr

Specifications of PIC12F1840T-I/SN

• Core Processor: RISC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 5
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.1.1.2
The program memory can be accessed as data by set-
ting bit 7 of the FSRxH register and reading the match-
ing INDFx register. The MOVIW instruction will place the
lower 8 bits of the addressed word in the W register.
Writes to the program memory cannot be performed via
the INDF registers. Instructions that access the pro-
gram memory via the FSR require one extra instruction
cycle to complete.
ing the program memory via an FSR.
The HIGH directive will set bit<7> if a label points to a
location in program memory.
EXAMPLE 3-2:
3.2
The data memory is partitioned in 32 memory banks
with 128 bytes in a bank. Each bank consists of
(Figure
• 12 core registers
• 20 Special Function Registers (SFR)
• Up to 80 bytes of General Purpose RAM (GPR)
• 16 bytes of common RAM
The active bank is selected by writing the bank number
into the Bank Select Register (BSR). Unimplemented
memory will read as ‘0’. All data memory can be
accessed either directly (via instructions that use the
file registers) or indirectly via the two File Select
Registers
Addressing”
 2011 Microchip Technology Inc.
constants
my_function
;THE PROGRAM MEMORY IS IN W
RETLW DATA0
RETLW DATA1
RETLW DATA2
RETLW DATA3
;… LOTS OF CODE…
MOVLW
MOVWF
MOVLW
MOVWF
MOVIW 0[FSR1]
3-2):
Data Memory Organization
(FSR).
Indirect Read with FSR
for more information.
LOW constants
FSR1L
HIGH constants
FSR1H
Example 3-2
ACCESSING PROGRAM
MEMORY VIA FSR
See
;Index0 data
;Index1 data
Section 3.5
demonstrates access-
“Indirect
Preliminary
3.2.1
The core registers contain the registers that directly
affect the basic operation of the PIC12(L)F1840. These
registers are listed below:
• INDF0
• INDF1
• PCL
• STATUS
• FSR0 Low
• FSR0 High
• FSR1 Low
• FSR1 High
• BSR
• WREG
• PCLATH
• INTCON
Note:
CORE REGISTERS
The core registers are the first 12
addresses of every data memory bank.
PIC12(L)F1840
DS41441B-page 17