PIC12F1840T-I/SN Microchip Technology, PIC12F1840T-I/SN Datasheet - Page 72

• Manufacturer Part Number: PIC12F1840T-I/SN
• Description: 7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core 8 SOI
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 12Fr

Specifications of PIC12F1840T-I/SN

• Core Processor: RISC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 5
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC12(L)F1840
7.3
The MCLR is an optional external input that can reset
the device. The MCLR function is controlled by the
MCLRE bit of Configuration Word 1 and the LVP bit of
Configuration Word 2
TABLE 7-2:
7.3.1
When MCLR is enabled and the pin is held low, the
device is held in Reset. The MCLR pin is connected to
V
The device has a noise filter in the MCLR Reset path.
The filter will detect and ignore small pulses.
7.3.2
When MCLR is disabled, the pin functions as a general
purpose input and the internal weak pull-up is under
software control. See Section 12.2 “PORTA Registers”
for more information.
7.4
The Watchdog Timer generates a Reset if the firmware
does not issue a CLRWDT instruction within the time-out
period. The TO and PD bits in the STATUS register are
changed to indicate the WDT Reset. See Section 10.0
“Watchdog Timer” for more information.
7.5
A RESET instruction will cause a device Reset. The RI
bit in the PCON register will be set to ‘0’. See
for default conditions after a RESET instruction has
occurred.
7.6
The device can reset when the Stack Overflows or
Underflows. The STKOVF or STKUNF bits of the PCON
register indicate the Reset condition. These Resets are
enabled by setting the STVREN bit in Configuration
Word 2.
Reset”
7.7
Upon exit of Programming mode, the device will
behave as if a POR had just occurred.
DS41441B-page 72
DD
Note:
through an internal weak pull-up.
MCLRE
for more information.
0
1
x
MCLR
Watchdog Timer (WDT) Reset
RESET Instruction
Stack Overflow/Underflow Reset
Programming Mode Exit
See
MCLR ENABLED
A Reset does not drive the MCLR pin low.
MCLR DISABLED
Section 3.4.2
MCLR CONFIGURATION
(Table
LVP
0
0
1
7-2).
“Overflow/Underflow
Disabled
Enabled
Enabled
MCLR
Table 7-4
Preliminary
7.8
The Power-up Timer optionally delays device execution
after a BOR or POR event. This timer is typically used to
allow V
running.
The Power-up Timer is controlled by the PWRTE bit of
Configuration Word 1.
7.9
Upon the release of a POR or BOR, the following must
occur before the device will begin executing:
1.
2.
3.
The total time-out will vary based on oscillator configu-
ration and
Section 5.0 “Oscillator Module (With Fail-Safe
Clock Monitor)”
The Power-up Timer and oscillator start-up timer run
independently of MCLR Reset. If MCLR is kept low long
enough, the Power-up Timer and oscillator start-up
timer will expire. Upon bringing MCLR high, the device
will begin execution immediately (see
is useful for testing purposes or to synchronize more
than one device operating in parallel.
Power-up Timer runs to completion (if enabled).
Oscillator start-up timer runs to completion (if
required for oscillator source).
MCLR must be released (if enabled).
DD
Power-Up Timer
Start-up Sequence
to stabilize before allowing the device to start
Power-up
for more information.
 2011 Microchip Technology Inc.
Timer
configuration.
Figure
7-4). This
See