PIC16F1827T-I/SO Microchip Technology, PIC16F1827T-I/SO Datasheet - Page 313

• Manufacturer Part Number: PIC16F1827T-I/SO
• Description: 7 KB Flash, 384 Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core 18 S
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1827T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 18-SOIC (7.5mm Width)
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25.4.2
The following bits are used to configure the EUSART
for Synchronous slave operation:
• SYNC = 1
• CSRC = 0
• SREN = 0 (for transmit); SREN = 1 (for receive)
• CREN = 0 (for transmit); CREN = 1 (for receive)
• SPEN = 1
Setting the SYNC bit of the TXSTA register configures the
device for synchronous operation. Clearing the CSRC bit
of the TXSTA register configures the device as a slave.
Clearing the SREN and CREN bits of the RCSTA register
ensures that the device is in the Transmit mode,
otherwise the device will be configured to receive. Setting
the SPEN bit of the RCSTA register enables the
EUSART.
25.4.2.1
The operation of the Synchronous Master and Slave
modes
“Synchronous Master Transmission”), except in the
case of the Sleep mode.
TABLE 25-9:
 2010 Microchip Technology Inc.
APFCON0
APFCON1
BAUDCON
INTCON
PIE1
PIR1
RCSTA
TRISB
TXREG
TXSTA
Legend:
Note 1:
Name
*
are
— = unimplemented location, read as ‘0’. Shaded cells are not used for Synchronous Slave Transmission.
Page provides register information.
PIC16F/LF1827 only.
SYNCHRONOUS SLAVE MODE
EUSART Synchronous Slave
Transmit
RXDTSEL
TMR1GIE
TMR1GIF
ABDOVF
TRISB7
CSRC
SPEN
Bit 7
identical
GIE
SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE
TRANSMISSION
—
SDO1SEL
TRISB6
RCIDL
PEIE
ADIE
ADIF
Bit 6
RX9
TX9
(see
—
Section 25.4.1.3
SS1SEL
TMR0IE
TRISB5
SREN
TXEN
RCIE
RCIF
Bit 5
—
—
EUSART Transmit Data Register
P2BSEL
TRISB4
Preliminary
CREN
SYNC
SCKP
Bit 4
INTE
TXIE
TXIF
—
(1)
CCP2SEL
ADDEN
TRISB3
SENDB
BRG16
SSPIE
SSPIF
IOCIE
If two words are written to the TXREG and then the
SLEEP instruction is executed, the following will occur:
1.
2.
3.
4.
5.
25.4.2.2
1.
2.
3.
4.
5.
6.
7.
8.
Bit 3
—
The first character will immediately transfer to
the TSR register and transmit.
The second word will remain in TXREG register.
The TXIF bit will not be set.
After the first character has been shifted out of
TSR, the TXREG register will transfer the second
character to the TSR and the TXIF bit will now be
set.
If the PEIE and TXIE bits are set, the interrupt
will wake the device from Sleep and execute the
next instruction. If the GIE bit is also set, the
program will call the Interrupt Service Routine.
Set the SYNC and SPEN bits and clear the
CSRC bit.
Clear the ANSEL bit for the CK pin (if applicable).
Clear the CREN and SREN bits.
If interrupts are desired, set the TXIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
If 9-bit transmission is desired, set the TX9 bit.
Enable transmission by setting the TXEN bit.
If 9-bit transmission is selected, insert the Most
Significant bit into the TX9D bit.
Start
Significant 8 bits to the TXREG register.
(1)
PIC16F/LF1826/27
P1DSEL
TMR0IF
CCP1IE
CCP1IF
TRISB2
BRGH
FERR
transmission
Bit 2
—
—
Synchronous Slave Transmission
Set-up:
P1CSEL
TMR2IE
TMR2IF
TRISB1
OERR
TRMT
WUE
INTF
Bit 1
—
by
writing
CCP1SEL
TXCKSEL
TMR1IE
TMR1IF
TRISB0
ABDEN
IOCIF
RX9D
TX9D
Bit 0
DS41391C-page 313
the
Register
on Page
289*
Least
122
122
298
101
102
105
297
129
296