PIC16F1847-I/SO Microchip Technology, PIC16F1847-I/SO Datasheet - Page 243

• Manufacturer Part Number: PIC16F1847-I/SO
• Description: 14 KB Flash, 1K Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core 18 S
• Manufacturer: Microchip Technology

Specifications of PIC16F1847-I/SO

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

25.2.6 SPI OPERATION IN SLEEP MODE
In SPI Master mode, module clocks may be operating
at a different speed than when in Full-Power mode; in
the case of the Sleep mode, all clocks are halted.
Special care must be taken by the user when the
MSSPx clock is much faster than the system clock.
In Slave mode, when MSSPx interrupts are enabled,
after the master completes sending data, an MSSPx
interrupt will wake the controller from Sleep.
If an exit from Sleep mode is not desired, MSSPx
interrupts should be disabled.
TABLE 25-1:
 2011 Microchip Technology Inc.
APFCON0
ANSELA
ANSELB
INTCON
PIE1
PIR1
SSP1BUF
SSP1CON1
SSP1CON3
SSP1STAT
SSP2BUF
SSP2CON1
SSP2CON3
SSP2STAT
TRISA
TRISB
Legend:
Name
*
— = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSPx in SPI mode.
Page provides register information.
Synchronous Serial Port Receive Buffer/Transmit Register
Synchronous Serial Port Receive Buffer/Transmit Register
RXDTSEL
TMR1GIE
TMR1GIF
ACKTIM
TRISA7
TRISB7
ANSB7
ACKTIM
WCOL
WCOL
Bit 7
SMP
SMP
GIE
—
SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION
SDO1SEL
SSPOV
TRISA6
TRISB6
ANSB6
SSPOV
ADIE
PCIE
Bit 6
PEIE
ADIF
CKE
PCIE
CKE
—
SS1SEL
TMR0IE
SSPEN
TRISA5
TRISB5
ANSB5
SSPEN
RCIE
RCIF
SCIE
Bit 5
SCIE
D/A
D/A
—
P2BSEL
TRISA4
TRISB4
ANSA4
ANSB4
BOEN
BOEN
Preliminary
INTE
TXIE
Bit 4
TXIF
CKP
CKP
P
P
CCP2SEL
SSP1IE
SSP1IF
TRISA3
TRISB3
ANSA3
ANSB3
SDAHT
SSPM3
SDAHT
IOCE
Bit 3
In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the transmis-
sion/reception will remain in that state until the device
wakes. After the device returns to Run mode, the mod-
ule will resume transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in Sleep mode and data
to be shifted into the SPI Transmit/Receive Shift
register. When all 8 bits have been received, the
MSSPx interrupt flag bit will be set and if enabled, will
wake the device.
S
S
P1DSEL
TMR0IF
CCP1IE
CCP1IF
SBCDE
TRISA2
TRISB2
ANSA2
ANSB2
SSPM2
SBCDE
Bit 2
R/W
R/W
SSPM<3:0>
PIC16(L)F1847
P1CSEL
TMR2IE
TMR2IF
TRISA1
TRISB1
ANSA1
ANSB1
SSPM1
AHEN
AHEN
Bit 1
INTF
UA
UA
CCP1SEL
TMR1IE
TMR1IF
TRISA0
TRISB0
ANSA0
SSPM0
DHEN
DHEN
IOCF
Bit 0
DS41453A-page 243
BF
—
BF
Register
on Page
237*
120
123
128
283
285
282
283
285
282
122
127
89
90
94
29