PIC16F707-I/MV Microchip Technology, PIC16F707-I/MV Datasheet
PIC16F707-I/MV
Specifications of PIC16F707-I/MV
Related parts for PIC16F707-I/MV
PIC16F707-I/MV Summary of contents
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... Flash Microcontrollers 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 with nanoWatt XLP and mTouch™ Technology Preliminary Data Sheet DS41418A ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... A/D Converter: - 8-bit resolution and channels - Conversion available during Sleep - Selectable 1.024V/2.048V/4.096V voltage reference • On-chip 3.2V Regulator (PIC16F707 device only) Peripheral Highlights: • I/O Pins and 1 Input-only Pin: - High current source/sink for direct LED drive - Interrupt-on-pin change - Individually programmable weak pull-ups • ...
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... CPSA6/AN6/RE1 CPSA7/AN7/RE2 CLKIN/OSC1/CPSB0/RA7 (3) V CLKOUT/OSC2/CPSB1/RA6 CAP / T1CKI/T1OSO/CPSB2/RC0 (1) CCP2 /T1OSI/CPSB3/RC1 TBCKI/CCP1/CPSB4/RC2 SCL/SCK/RC3 T3G/CPSB5/RD0 CPSB6/RD1 Note 1: CCP2 pin location may be selected as RB3 or RC1 pin location may be selected as RA5 or RA0. 3: PIC16F707 only. DS41418A-page 4 Capacitive Touch 8-bit A/D I/Os Channels (ch RB7/CPSB15/ICSPDAT 1 40 RB6/CPSB14/ICSPCLK 39 2 RB5/AN13/CPSB13/T1G/T3CKI 38 3 ...
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... Pin Diagrams 44-PIN QFN (8x8x0.9) DT/RX/CPSA11/RC7 CPSA12/RD4 CPSA13/RD5 CPSA14/RD6 CPSA15/RD7 INT/CPSB8/AN12/RB0 CPSB9/AN10/RB1 CPSB10/AN8/RB2 Note 1: CCP2 pin location may be selected as RB3 or RC1 pin location may be selected as RA5 or RA0. 3: PIC16F707 only. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 1 RA6/OSC2/CLKOUT/CPSB1 RA7/OSC1/CLKIN/CPSB0 PIC16F707 PIC16LF707 7 RE2/AN7/CPSA7 27 8 RE1/AN6/CPSA6 ...
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... PIC16F707/PIC16LF707 Pin Diagrams 44-PIN TQFP DT/RX/CPSA11/RC7 CPSA12/RD4 CPSA13/RD5 CPSA14/RD6 CPSA15/RD7 INT/CPSB8/AN12/RB0 CPSB9/AN10/RB1 CPSB10/AN8/RB2 (1) CCP2 /CPSB11/AN9/RB3 Note 1: CCP2 pin location may be selected as RB3 or RC1 pin location may be selected as RA5 or RA0. 3: PIC16F707 only. DS41418A-page RC0/T1OSO/T1CKI/CPSB2 31 3 RA6/OSC2/CLKOUT/CPSB1 RA7/OSC1/CLKIN/CPSB0 PIC16F707 PIC16LF707 27 RE2/AN7/CPSA7 7 RE1/AN6/CPSA6 8 26 ...
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... TABLE 1: 40/44-PIN ALLOCATION TABLE FOR PIC16F707/PIC16LF707 RA0 AN0 RA1 AN1 RA2 AN2 RA3 AN3/ V REF RA4 — RA5 AN4 RA6 — RA7 — RB0 AN12 RB1 AN10 RB2 AN8 RB3 AN9 RB4 AN11 RB5 AN13 RB6 — RB7 — RC0 15 32 ...
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... PIC16F707/PIC16LF707 Table of Contents 1.0 Device Overview ....................................................................................................................................................................... 11 2.0 Memory Organization ................................................................................................................................................................ 17 3.0 Resets ....................................................................................................................................................................................... 29 4.0 Interrupts ................................................................................................................................................................................... 39 5.0 Low Dropout (LDO) Voltage Regulator ..................................................................................................................................... 49 6.0 I/O Ports .................................................................................................................................................................................... 51 7.0 Oscillator Module....................................................................................................................................................................... 69 8.0 Device Configuration ................................................................................................................................................................. 75 9.0 Analog-to-Digital Converter (ADC) Module ............................................................................................................................... 79 10.0 Fixed Voltage Reference ........................................................................................................................................................... 89 11.0 Digital-to-Analog Converter (DAC) Module ............................................................................................................................... 91 12 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 Preliminary DS41418A-page 9 ...
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... PIC16F707/PIC16LF707 NOTES: DS41418A-page 10 Preliminary 2010 Microchip Technology Inc. ...
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... DEVICE OVERVIEW The PIC16F707/PIC16LF707 devices are covered by this data sheet. They are available in 40/44-pin packages. Figure 1-1 shows a block diagram of the PIC16F707/PIC16LF707 devices. Table 1-1 shows the pinout descriptions. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 Preliminary DS41418A-page 11 ...
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... PIC16F707/PIC16LF707 FIGURE 1-1: PIC16F707/PIC16LF707 BLOCK DIAGRAM Configuration Configuration Configuration Program Counter Program Counter Program Counter Flash Program Memory Program Program Program Bus Bus Bus Instruction Reg Instruction reg Instruction reg Direct Addr Direct Addr Instruction Instruction Instruction Start-up Timer Start-up Timer Decode and Decode & ...
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... TABLE 1-1: PIC16F707/PIC16LF707 PINOUT DESCRIPTION Name Function RA0/AN0/SS/V RA0 CAP AN0 SS V CAP RA1/AN1/CPSA0 RA1 AN1 CPSA0 RA2/AN2/CPSA1/DACOUT RA2 AN2 CPSA1 DACOUT RA3/AN3/V /CPSA2 RA3 REF AN3 V REF CPSA2 RA4/CPSA3/T0CKI/TACKI RA4 CPSA3 T0CKI TACKI RA5/AN4/CPSA4/SS/V RA5 CAP AN4 CPSA4 SS V CAP ...
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... PIC16F707/PIC16LF707 TABLE 1-1: PIC16F707/PIC16LF707 PINOUT DESCRIPTION (CONTINUED) Name Function RB2/AN8/CPSB10 RB2 AN8 CPSB10 RB3/AN9/CPSB11/CCP2 RB3 AN9 CPSB11 CCP2 RB4/AN11/CPSB12 RB4 AN11 CPSB12 RB5/AN13/CPSB13/T1G/T3CKI RB5 AN13 CPSB13 T1G T3CKI RB6/ICSPCLK/ICDCLK/CPSB14 RB6 ICSPCLK ICDCLK CPSB14 RB7/ICSPDAT/ICDDAT/CPSB15 RB7 ICSPDAT ICDDAT CPSB15 RC0/T1OSO/T1CKI/CPSB2 RC0 T1OSO ...
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... TABLE 1-1: PIC16F707/PIC16LF707 PINOUT DESCRIPTION (CONTINUED) Name Function RC4/SDI/SDA RC4 SDI SDA RC5/SDO/CPSA9 RC5 SDO CPSA9 RC6/TX/CK/CPSA10 RC6 TX CK CPSA10 RC7/RX/DT/CPSA11 RC7 RX DT CPSA11 RD0/CPSB5/T3G RD0 CPSB5 T3G RD1/CPSB6 RD1 CPSB6 RD2/CPSB7 RD2 CPSB7 RD3/CPSA8 RD3 CPSA8 RD4/CPSA12 RD4 CPSA12 RD5/CPSA13 ...
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... TTL = TTL compatible input HV = High Voltage Note: The PIC16F707 devices have an internal low dropout voltage regulator. An external capacitor must be connected to one of the available V Section 5.0 “Low Dropout (LDO) Voltage Regulator”. The PIC16LF707 devices do not have the voltage regulator and therefore no external capacitor is required. ...
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... MEMORY ORGANIZATION 2.1 Program Memory Organization The PIC16F707/PIC16LF707 has a 13-bit program counter capable of addressing program memory space. The Reset vector is at 0000h and the interrupt vector is at 0004h. FIGURE 2-1: PROGRAM MEMORY MAP AND STACK FOR THE PIC16F707/PIC16LF707 PC<12:0> CALL, RETURN ...
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... PIC16F707/PIC16LF707 TABLE 2-1: DATA MEMORY MAP FOR PIC16F707/PIC16LF707 (*) Indirect addr. 00h Indirect addr. TMR0 01h OPTION PCL 02h PCL STATUS 03h STATUS FSR 04h FSR PORTA 05h TRISA PORTB 06h TRISB PORTC 07h TRISC PORTD 08h TRISD PORTE 09h TRISE PCLATH ...
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... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: Accessible only when SSPM<3:0> = 1001. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 Bit 5 Bit 4 Bit 3 Bit 2 Timer0 Module Register Program Counter (PC) Least Significant Byte ...
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... PIC16F707/PIC16LF707 TABLE 2-2: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Bank 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 81h OPTION_REG RBPU INTEDG ( 2) 82h PCL ( 2) 83h STATUS IRP RP1 ( 2) 84h FSR 85h TRISA ...
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... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the upper byte of the program counter. 2: These registers can be addressed from any bank. 3: Accessible only when SSPM<3:0> = 1001. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 Bit 5 Bit 4 Bit 3 Bit 2 Timer0 Module Register Program Counter’s (PC) Least Significant Byte ...
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... PIC16F707/PIC16LF707 TABLE 2-2: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Address Name Bit 7 Bit 6 Bank 180h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 181h OPTION_REG RBPU INTEDG ( 2) 182h PCL ( 2) 183h STATUS IRP RP1 ( 2) 184h FSR 185h ANSELA ...
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... For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order bit of the source register. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as ‘ ...
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... PIC16F707/PIC16LF707 2.2.2.2 OPTION register The OPTION register, shown in Register 2- readable and writable register, which contains various control bits to configure: • Timer0/WDT prescaler • External RB0/INT interrupt • Timer0 • Weak pull-ups on PORTB REGISTER 2-2: OPTION_REG: OPTION REGISTER R/W-1 R/W-1 R/W-1 RBPU ...
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... A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 U-0 U-0 U-0 — — — ...
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... PIC16F707/PIC16LF707 2.3 PCL and PCLATH The Program Counter (PC bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from PCLATH. On any Reset, the PC is cleared. Figure 2-2 shows the two situations for the loading of the PC ...
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... From Opcode RP1 RP0 6 Bank Select Location Select 00h Data Memory 7Fh Bank 0 Note: For memory map detail, refer to Table 2-2. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 EXAMPLE 2-2: MOVLW MOVWF BANKISEL NEXT CLRF INCF BTFSS GOTO CONTINUE 0 IRP Bank Select 00 ...
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... PIC16F707/PIC16LF707 NOTES: DS41418A-page 28 Preliminary 2010 Microchip Technology Inc. ...
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... RESETS The PIC16F707/PIC16LF707 differentiates between various kinds of Reset: a) Power-on Reset (POR) b) WDT Reset during normal operation c) WDT Reset during Sleep d) MCLR Reset during normal operation e) MCLR Reset during Sleep f) Brown-out Reset (BOR) Some registers are not affected in any Reset condition; ...
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... PIC16F707/PIC16LF707 TABLE 3-1: STATUS BITS AND THEIR SIGNIFICANCE POR BOR TO PD Power-on Reset or LDO Reset Illegal set on POR Illegal set on POR Brown-out Reset WDT Reset WDT Wake- MCLR Reset during normal operation MCLR Reset during Sleep or interrupt wake-up from Sleep TABLE 3-2: ...
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... MCLR The PIC16F707/PIC16LF707 has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a Reset does not drive the MCLR pin low. Voltages applied to the pin that exceed its specification can result in both MCLR Resets and excessive current beyond the device specification during the ESD event ...
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... PIC16F707/PIC16LF707 3.4.2 WDT CONTROL The WDTE bit is located in the Configuration Word Register 1. When set, the WDT runs continuously. The PSA and PS<2:0> bits of the OPTION register control the WDT period. See Section 12.0 “Timer0 Module” for more information. FIGURE 3-3: ...
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... DD Internal Reset V DD Internal Reset Note delay only if PWRTE bit is programmed to ‘0’. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 If V falls below V DD BOR (T ) (see Section 25.0 “Electrical Specifica- BOR tions”), the brown-out situation will reset the device. This will occur regardless of V ...
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... Configuration Word register). Bit 1 is POR (Power-on Reset ‘0’ on Power-on Reset and unaffected otherwise. The user must write a ‘1’ to this bit following a Power-on Reset PIC16F707/ subsequent Reset, if POR is ‘0’, it will indicate that a Power-on Reset has occurred (i.e., V gone too low). ...
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... TIME-OUT SEQUENCE ON POWER-UP (DELAYED MCLR): CASE MCLR Internal POR PWRT Time-out OST Time-out Internal Reset FIGURE 3-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR WITH MCLR Internal POR PWRT Time-out OST Time-out Internal Reset 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 T PWRT T OST DD T PWRT T OST Preliminary ): CASE 3 DS41418A-page 35 ...
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... PIC16F707/PIC16LF707 TABLE 3-5: INITIALIZATION CONDITION FOR REGISTERS Power-on Reset/ Register Address Brown-out Reset W — xxxx xxxx INDF 00h/80h/ xxxx xxxx 100h/180h TMR0 01h/101h xxxx xxxx PCL 02h/82h/ 0000 0000 102h/182h STATUS 03h/83h/ 0001 1xxx 103h/183h FSR 04h/84h/ xxxx xxxx 104h/184h PORTA ...
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... When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 4: See Table 3-2 for Reset value for specific condition Reset was due to brown-out, then bit All other Resets will cause bit 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 MCLR Reset/ (1) WDT Reset --00 0000 1111 1111 1111 1111 ...
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... PIC16F707/PIC16LF707 TABLE 3-5: INITIALIZATION CONDITION FOR REGISTERS (CONTINUED) Power-on Reset/ Register Address Brown-out Reset TBCON 111h 0-00 0000 TMRB 112h 0000 0000 DACCON0 113h 000- 00-- DACCON1 114h ---0 0000 ANSELA 185h 1111 1111 ANSELB 186h 1111 1111 ANSELC 187h 1111 1111 ANSELD ...
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... An Interrupt Service Routine (ISR) is used to determine the source of the interrupt and act accordingly. Some interrupts can be configured to wake the MCU from Sleep mode. The PIC16F707 family has 16 interrupt sources, differentiated by corresponding interrupt enable and flag bits: • Timer0 Overflow Interrupt • ...
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... PIC16F707/PIC16LF707 4.1 Operation Interrupts are disabled upon any device Reset. They are enabled by setting the following bits: • GIE bit of the INTCON register • Interrupt enable bit(s) for the specific interrupt event(s) • PEIE bit of the INTCON register (if the interrupt enable bit of the interrupt event is contained in the ...
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... W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 following the ISR from using invalid data. Examples of key registers include the W, STATUS, FSR and PCLATH registers. Note: The microcontroller does not normally require saving the PCLATH register. ...
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... PIC16F707/PIC16LF707 4.5.1 INTCON REGISTER The INTCON register is a readable and writable register, which contains the various enable and flag bits for TMR0 register overflow, PORTB change and external RB0/INT/SEG0 pin interrupts. REGISTER 4-1: INTCON: INTERRUPT CONTROL REGISTER R/W-0 R/W-0 R/W-0 GIE ...
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... Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 Note: Bit PEIE of the INTCON register must be set to enable any peripheral interrupt. R/W-0 R/W-0 ...
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... PIC16F707/PIC16LF707 4.5.3 PIE2 REGISTER The PIE2 register contains the interrupt enable bits, as shown in Register 4-3. REGISTER 4-3: PIE2 – PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 R/W-0 TMR3GIE TMR3IE TMRBIE bit 7 Legend Readable bit W = Writable bit u = bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘ ...
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... TMR1IF: Timer1 Overflow Interrupt Flag bit 1 = The Timer1 register overflowed (must be cleared in software The Timer1 register did not overflow 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE of the INTCON register ...
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... PIC16F707/PIC16LF707 4.5.5 PIR2 REGISTER The PIR2 register contains the interrupt flag bits, as shown in Register 4-5. REGISTER 4-5: PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2 R/W-0 R/W-0 R/W-0 TMR3GIF TMR3IF TMRBIF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 ...
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... TMR3GIE TMR3IE TMRBIE PIR1 TMR1GIF ADIF PIR2 TMR3GIF TMR3IF TMRBIF Legend Unimplemented locations, read as ‘0’ unchanged unknown. Shaded cells are not used by interrupts. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 Bit 5 Bit 4 Bit 3 Bit 2 INTE RBIE TMR0IF PSA PS2 TXIE SSPIE ...
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... PIC16F707/PIC16LF707 NOTES: DS41418A-page 48 Preliminary 2010 Microchip Technology Inc. ...
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... LOW DROPOUT (LDO) VOLTAGE REGULATOR The PIC16F707 has an internal Low Dropout Regulator (LDO) which provides operation above 3.6V. The LDO regulates a voltage for the internal device logic while permitting the V and I/O pins to operate at a higher DD voltage. There is no user enable/disable control available for the LDO always active ...
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... PIC16F707/PIC16LF707 NOTES: DS41418A-page 50 Preliminary 2010 Microchip Technology Inc. ...
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... SSSEL: SS Input Pin Selection bit function is on RA5/AN4/CPS7/SS function is on RA0/AN0/SS/V bit 0 CCP2SEL: CCP2 Input/Output Pin Selection bit 0 = CCP2 function is on RC1/T1OSI/CCP2 1 = CCP2 function is on RB3/CCP2 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 FIGURE 6-1: GENERIC I/O PORT OPERATION D Q Write PORTx CK ...
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... PIC16F707/PIC16LF707 6.2 PORTA and TRISA Registers PORTA is a 8-bit wide, bidirectional port. The corresponding data direction register is TRISA (Register 6-3). Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., disable the output driver). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i ...
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... The RA0 pin is configurable to function as one of the following: • General purpose I/O • Analog input for the A/D (1) • Slave Select input for the SSP • Voltage Regulator Capacitor pin (PIC16F707 only) Note 1: SS pin location may be selected as RA5 or RA0. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 ...
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... RA6/CPSB1/OSC2/CLKOUT/V The RA6 pin is configurable to function as one of the following: • General purpose I/O • Crystal/resonator connection • Clock Output • Voltage Regulator Capacitor pin (PIC16F707 only) • Capacitive sensing input 6.2.2.8 RA7/CPSB0/OSC1/CLKIN The RA7 pin is configurable to function as one of the following: • ...
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... The ANSELB register must be initialized to configure an analog channel as a digital input. Pins configured as analog inputs will read ‘0’. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 6.3.1 ANSELB REGISTER The ANSELB register (Register 6-9) is used to configure the Input mode of an I/O pin to analog. ...
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... PIC16F707/PIC16LF707 REGISTER 6-5: PORTB: PORTB REGISTER R/W-x R/W-x R/W-x RB7 RB6 RB5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 RB<7:0>: PORTB I/O Pin bit 1 = Port pin is > Port pin is < REGISTER 6-6: TRISB: PORTB TRI-STATE REGISTER ...
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... These pins are configurable to function as one of the following: • General purpose I/O • Analog input for the ADC • Capacitive sensing input • External edge triggered interrupt 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 R/W-0 R/W-0 R/W-0 IOCB4 IOCB3 IOCB2 U = Unimplemented bit, read as ‘0’ ...
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... PIC16F707/PIC16LF707 6.3.4.4 RB3/AN9/CPSB11/CCP2 These pins are configurable to function as one of the following: • General purpose I/O • Analog input for the ADC • Capacitive sensing input • Capture 2 input, Compare 2 output, and PWM2 output Note: CCP2 pin location may be selected as RB3 or RC1. ...
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... W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 TRISC<7:0>: PORTC Tri-State Control bits 1 = PORTC pin configured as an input (tri-stated PORTC pin configured as an output 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 EXAMPLE 6-3: BANKSEL PORTC CLRF PORTC is TRISC BANKSEL TRISC MOVLW B‘ ...
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... PIC16F707/PIC16LF707 6.4.1 ANSELC REGISTER The ANSELC register (Register 6-12) is used to configure the Input mode of an I/O pin to analog. Setting the appropriate ANSELC bit high will cause all digital reads on the pin to be read as ‘0’ and allow analog functions on the pin to operate correctly. ...
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... TRISC7 TRISC6 TRISC5 Legend unknown unchanged unimplemented locations read as ‘0’. Shaded cells are not used by PORTC. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 6.4.2.6 These pins are configurable to function as one of the following: • General purpose I/O • SPI data output • Capacitive sensing input 6 ...
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... PIC16F707/PIC16LF707 6.5 PORTD and TRISD Registers PORTD is a 8-bit wide, bidirectional port. The corresponding data direction register (Register 6-14). Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i ...
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... Timer3 Gate input 6.5.2.2 RD1/CPSB6 These pins are configurable to function as one of the following: • General purpose I/O • Capacitive sensing input 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 R/W-1 R/W-1 R/W-1 TRISD4 TRISD3 TRISD2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
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... PIC16F707/PIC16LF707 6.5.2.6 RD5/CPSA13 These pins are configurable to function as one of the following: • General purpose I/O • Capacitive sensing input 6.5.2.7 RD6/CPSA14 These pins are configurable to function as one of the following: • General purpose I/O • Capacitive sensing input TABLE 6-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD ...
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... Bit is set bit 7-4 Unimplemented: Read as ‘0’ bit 3-0 RE<3:0>: PORTE I/O Pin bits 1 = Port pin is > Port pin is < 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 EXAMPLE 6-5: INITIALIZING PORTE BANKSEL PORTE CLRF PORTE BANKSEL ANSELE CLRF ANSELE BANKSEL TRISE MOVLW B‘ ...
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... PIC16F707/PIC16LF707 REGISTER 6-17: TRISE: PORTE TRI-STATE REGISTER U-0 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-4 Unimplemented: Read as ‘0’ bit 3 TRISE3: RE3 Port Tri-state Control bit This bit is always ‘1’ as RE3 is an input only bit 2-0 TRISE< ...
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... Legend unknown unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by PORTE. Note 1: This bit is always ‘1’ as RE3 is input only. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 Bit 4 Bit 3 Bit 2 Bit 1 CHS2 CHS1 CHS0 GO/DONE — ...
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... PIC16F707/PIC16LF707 NOTES: DS41418A-page 68 Preliminary 2010 Microchip Technology Inc. ...
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... PLL PLLEN (Configuration Word 1) 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 Clock source modes are configured by the FOSC bits in Configuration Word 1 (CONFIG1). The oscillator module can be configured for one of eight modes of operation – External Resistor-Capacitor (RC) with F /4 output on OSC2/CLKOUT. ...
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... PIC16F707/PIC16LF707 7.2 Clock Source Modes Clock source modes can be classified as external or internal. • Internal clock source (INTOSC) is contained within the oscillator module and derived from a 500 kHz high precision oscillator. The oscillator module has eight selectable output frequencies, with a maximum internal frequency of 16 MHz. ...
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... ICSS: Internal Clock Oscillator Status Stable bit (0.5% Stable MHz/500 kHz Internal Oscillator (HFIOSC) has stabilized to its maximum accuracy MHz/500 kHz Internal Oscillator (HFIOSC) has not yet reached its maximum accuracy bit 1-0 Unimplemented: Read as ‘0’ 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 clock. The R/W-0 R-q R-q ...
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... PIC16F707/PIC16LF707 7.5 Oscillator Tuning The INTOSC is factory calibrated but can be adjusted in software by writing to the OSCTUNE register (Register 7-2). The default value of the OSCTUNE register is ‘0’. The value is a 6-bit two’s complement number. REGISTER 7-2: OSCTUNE: OSCILLATOR TUNING REGISTER U-0 ...
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... This mode is best suited to drive resonators with a low drive level specification, for example, tuning fork type crystals. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 XT Oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. XT mode current consumption is the medium of the three modes. ...
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... PIC16F707/PIC16LF707 FIGURE 7-4: CERAMIC RESONATOR OPERATION ( MODE) PIC OSC1/CLKIN C1 P ( OSC2/CLKOUT C2 Ceramic S (1) R Resonator Note 1: A series resistor (R ) may be required for S ceramic resonators with low drive level. 2: The value of R varies with the Oscillator mode F selected additional parallel feedback resistor (R may be required for proper ceramic resonator operation ...
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... When MCLR is asserted in INTOSC or RC mode, the internal clock oscillator is disabled. ® 4: MPLAB IDE masks unimplemented Configuration bits to ‘0’. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 8.1 Configuration Words There are several Configuration Word bits that allow different oscillator and memory protection options. These are implemented as Configuration Word 1 register at 2007h and Configuration Word 2 register at 2008h ...
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... Value at POR ‘1’ = Bit is set bit 15-6 Unimplemented: Read as ‘1’ bit 5-4 VCAPEN<1:0>: Voltage Regulator Capacitor Enable bits For the PIC16LF707: These bits are ignored. All V For the PIC16F707 functionality is enabled on RA0 CAP functionality is enabled on RA5 CAP functionality is enabled on RA6 ...
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... ICSP™ for verification purposes. Note: The entire Flash program memory will be erased when the code protection is turned off. See the “PIC16F707/PIC16LF707 Memory Programming (DS41332) for more information. 8.3 User ID Four memory locations (2000h-2003h) are designated as ID locations where the user can store checksum or other code identification numbers ...
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... PIC16F707/PIC16LF707 NOTES: DS41418A-page 78 Preliminary 2010 Microchip Technology Inc. ...
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... REF AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 Reserved FV REF CHS<3:0> 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 (ADC) allows AV DD ADREF = 0x ADREF = 11 + ADREF = 10 0000 0001 0010 0011 0100 0101 0110 0111 ADC 1000 GO/DONE ...
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... PIC16F707/PIC16LF707 9.1 ADC Configuration When configuring and using the ADC the following functions must be considered: • Port configuration • Channel selection • ADC voltage reference selection • ADC conversion clock source • Interrupt control • Results formatting 9.1.1 PORT CONFIGURATION The ADC can be used to convert both analog and digital signals ...
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... GIE and PEIE bits of the INTCON register must be disabled. If the GIE and PEIE bits of the INTCON register are enabled, execution will switch to the Interrupt Service Routine. Please refer to Section 9.1.5 “Interrupts” for more information. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 CYCLES ...
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... PIC16F707/PIC16LF707 9.2 ADC Operation 9.2.1 STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’. Setting the GO/ DONE bit of the ADCON0 register to a ‘1’ will start the Analog-to-Digital conversion. Note: The GO/DONE bit should not be set in the same instruction that turns on the ADC. Refer to Section 9.2.6 “ ...
Page 83
... MOVLW B’00000001’;AN0, On MOVWF ADCON0 ; CALL SampleTime ;Acquisiton delay BSF ADCON0,GO ;Start conversion BTFSC ADCON0,GO ;Is conversion done? GOTO $-1 ;No, test again BANKSEL ADRES ; MOVF ADRES,W ;Read result MOVWF RESULT ;store in GPR space 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 Preliminary DS41418A-page 83 ...
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... PIC16F707/PIC16LF707 9.2.7 ADC REGISTER DEFINITIONS The following registers are used to control the operation of the ADC. REGISTER 9-1: ADCON0: A/D CONTROL REGISTER 0 U-0 U-0 R/W-0 — — CHS3 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-6 Unimplemented: Read as ‘ ...
Page 85
... R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-0 ADRES<7:0>: ADC Result Register bits 8-bit conversion result. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 R/W-0 U-0 U-0 ADCS0 — — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
Page 86
... PIC16F707/PIC16LF707 9.3 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (C ) must be allowed to fully HOLD charge to the input channel voltage level. The analog input model is shown in Figure 9-3. The source impedance (R ) and the internal sampling switch (R ...
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... Threshold Voltage T Note 1: Refer to Section 25.0 “Electrical Specifications” FIGURE 9-4: ADC TRANSFER FUNCTION FFh FEh FDh FCh FBh 04h 03h 02h 01h 00h V SS 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 V DD Sampling Switch 0. Rss R IC LEAKAGE (1) I 0. ...
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... PIC16F707/PIC16LF707 TABLE 9-2: SUMMARY OF ASSOCIATED ADC REGISTERS Name Bit 7 Bit 6 Bit 5 ADCON0 — — CHS3 ADCON1 — ADCS2 ADCS1 ANSELA ANSA7 ANSA6 ANSA5 ANSELB ANSB7 ANSB6 ANSB5 ANSELE — — — ADRES CCP2CON — — DC2B1 FVRCON FVRRDY FVREN — INTCON ...
Page 89
... VOLTAGE REFERENCE BLOCK DIAGRAM FIGURE 10-1: ADFVR<1:0> CDAFVR<1:0> FVREN FVRRDY 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 10.1 Independent Gain Amplifiers The output of the FVR supplied to the ADC and CSM/DAC modules is routed through the two with 1.024V, independent programmable gain amplifiers. Each amplifier can be configured to amplify the reference voltage by 1x ...
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... A/D Converter Fixed Voltage Reference Peripheral output is 1x (1.024V A/D Converter Fixed Voltage Reference Peripheral output is 2x (2.048V A/D Converter Fixed Voltage Reference Peripheral output is 4x (4.096V) Note 1: FVRRDY is always ‘1’ on PIC16F707 devices. 2: Fixed Voltage Reference output cannot exceed V TABLE 10-1: ...
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... Reading the DACOUT pin when it has been configured for reference voltage output will always return a ‘0’. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 11.1 Output Voltage Selection The DAC has 32 voltage level ranges. The 32 levels are set with the DACR<4:0> bits of the DACCON1 register ...
Page 92
... PIC16F707/PIC16LF707 FIGURE 11-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM DACEN DACLPS DACPSS[1: DACPSS[1: REF DACPSS[1: FVR BUFFER 2 DACEN DACLPS EXAMPLE 11-1: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC16F707/ PIC16LF707 DAC R Module Voltage Reference Output Impedance DS41418A-page 92 DACR<4:0> Steps DACOUT – Preliminary (To Capacitive Sensing Module) ...
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... Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 DACR<4:0>: DAC Voltage Output Select bits 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 U-0 R/W-0/0 R/W-0/0 DACPSS1 DACPSS0 — Unimplemented bit, read as ‘0’ ...
Page 94
... PIC16F707/PIC16LF707 TABLE 11-1: REGISTERS ASSOCIATED WITH THE DIGITAL-TO-ANALOG CONVERTER Name Bit 7 Bit 6 Bit 5 FVRCON FVRRDY FVREN Reserved DACCON0 DACEN DACLPS DACOE DACCON1 — — — Legend: — = Unimplemented locations, read as ‘0’. Shaded cells are not used by the DAC module. DS41418A-page 94 ...
Page 95
... T0CKI pin 1 TMR0SE TMR0CS T1GSS = 11 TMR1GE WDTE Note 1: TMR0SE, TMR0CS, PSA, PS<2:0> are bits in the OPTION register. 2: WDTE bit is in Configuration Word 1. 3: T1GSS and TMR1GE are in the T1GCON register. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 8-bit Prescaler PSA 1 PSA 8 PS<2:0> 1 ...
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... PIC16F707/PIC16LF707 12.1 Timer0 Operation The Timer0 module can be used as either an 8-bit timer or an 8-bit counter. 12.1.1 8-BIT TIMER MODE The Timer0 module will increment every instruction cycle, if used without a prescaler. 8-bit Timer mode is selected by clearing the TMR0CS bit of the OPTION register. ...
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... TMR0CS TMR0 TRISA TRISA7 TRISA6 TRISA5 Legend: – = Unimplemented locations, read as ‘0’. Shaded cells are not used by the Timer0 module. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 R/W-1 R/W-1 R/W-1 TMR0SE PSA U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared /4) ...
Page 98
... PIC16F707/PIC16LF707 NOTES: DS41418A-page 98 Preliminary 2010 Microchip Technology Inc. ...
Page 99
... Special Event Trigger with CCP (Timer1 only) • Selectable Gate Source Polarity • Gate Toggle mode • Gate Single-pulse mode • Gate Value Status • Gate Event Interrupt Figure 13 block diagram of the Timer1/3 modules. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 Preliminary DS41418A-page 99 ...
Page 100
... PIC16F707/PIC16LF707 FIGURE 13-1: TIMER1/TIMER3 BLOCK DIAGRAM TxGSS<1:0> TxG 00 From TimerA/B 01 TxG_IN (4) Overflow From Timer2 10 Match PR2 From WDT 11 Overflow TxGPOL TxGTM Set flag bit TMRxIF on Overflow TMRx TMRxH T1OSO/T1CKI OUT (6) T1OSC T1OSI EN T1OSCEN (1) TxCKI Note 1: ST Buffer is high speed type when using TxCKI. ...
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... Microchip Technology Inc. PIC16F707/PIC16LF707 13.2 Clock Source Selection The TMRxCS<1:0> bits of the TxCON register and the T1OSCEN bit of the T1CON register are used to select the clock source for Timer1/3. Table 13-3 displays the clock source selections. 13.2.1 INTERNAL CLOCK SOURCE ...
Page 102
... PIC16F707/PIC16LF707 13.3 Timer1/3 Prescaler Timer1 and Timer3 have four prescaler options allowing divisions of the clock input. The TxCKPS bits of the TxCON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMRxH or TMRxL. ...
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... WDTE TxGSS = 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 Timer3 Gate Pin Overflow of TimerB (TMRB increments from FFh to 00h) Timer2 match PR2 (TMR2 increments to match PR2) Count Enabled by WDT Overflow (Watchdog Time-out interval expired) 13.6.6 WATCHDOG OVERFLOW GATE OPERATION The Watchdog Timer oscillator, prescaler and counter ...
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... PIC16F707/PIC16LF707 13.6.7 TIMER1/3 GATE TOGGLE MODE When Timer1/3 Gate Toggle mode is enabled possible to measure the full-cycle length of a Timer1/3 gate signal, as opposed to the duration of a single level pulse. The Timer1/3 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal ...
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... Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 In Capture mode, the value in the TMR1H:TMR1L register pair is copied into the CCPR1H:CCPR1L register pair on a configured event. ...
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... PIC16F707/PIC16LF707 FIGURE 13-3: TIMER1/TIMER3 GATE COUNT ENABLE MODE TMRxGE TxGPOL TxG_IN TxCKI TxGVAL Timer1/3 N FIGURE 13-4: TIMER1/TIMER3 GATE TOGGLE MODE TMRxGE TxGPOL TxGTM TxG_IN TxCKI TxGVAL TIMER1 DS41418A-page 106 Preliminary 2010 Microchip Technology Inc ...
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... TIMER1/TIMER3 GATE SINGLE-PULSE MODE TMRxGE TxGPOL TxGSPM TxGGO/ Set by software DONE Counting enabled on rising edge of TxG TxG_IN TxCKI TxGVAL TIMER1/3 N Cleared by software TMRxGIF 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 Cleared by hardware on falling edge of TxGVAL Set by hardware on falling edge of TxGVAL Preliminary Cleared by software DS41418A-page 107 ...
Page 108
... PIC16F707/PIC16LF707 FIGURE 13-6: TIMER1/TIMER3 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMRxGE TxGPOL TxGSPM TxGTM TxGGO/ Set by software DONE Counting enabled on rising edge of TxG TxG_IN TxCKI TxGVAL TIMER1/3 N Cleared by software TMRxGIF DS41418A-page 108 Set by hardware on falling edge of TxGVAL Preliminary 2010 Microchip Technology Inc. ...
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... This bit is ignored. Timerx uses the internal clock when TMR1CS<1:0> = 0X. bit 1 Unimplemented: Read as ‘0’ bit 0 TMRxON: Timerx on bit 1 = Enables Timerx 0 = Stops Timerx Clears Timerx gate flip-flop 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 R/W-0/0 R/W-0/0 R/W-0/0 (1) TxCKPS0 T1OSCEN TxSYNC U = Unimplemented bit, read as ‘0’ ...
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... PIC16F707/PIC16LF707 REGISTER 13-2: TxGCON: TIMER1/TIMER3 GATE CONTROL REGISTER R/W-0/0 R/W-0/0 R/W-0/0 TMRxGE TxGPOL TxGTM bit 7 Legend Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 TMRxGE: Timerx Gate Enable bit If TMRxON = 0: This bit is ignored. ...
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... BLOCK DIAGRAM OF THE TIMERA/TIMERB PRESCALER F /4 OSC TxCKI 0 pin 0 1 From 1 CPSxOSC TMRxCS TMRxSE TxXCS Note 1: TxXCS is in the CPSxCON0 register. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 1 Sync 2 Tcy 0 8-bit Prescaler TMRxPSA 8 TMRxPS<2:0> Preliminary Data Bus 8 TMRx Set Flag bit TMRxIF on Overflow Overflow to Timer1/3 ...
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... PIC16F707/PIC16LF707 14.1 TimerA/B Operation The TimerA/B modules can be used as either 8-bit tim- ers or 8-bit counters. Additionally, the modules can also be used to set Timer1’s/Timer3’s period of measure- ment for the capacitive sensing modules via Timer1’s or Timer3’s gate feature. TABLE 14-1: ...
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... TRISA5 TRISC TRISC7 TRISC6 TRISC5 Legend: – = Unimplemented locations, read as ‘0’. Shaded cells are not used by the TimerA/B modules. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 R/W-0/0 R/W-0/0 R/W-0/0 TMRxSE TMRxPSA TMRxPS2 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
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... PIC16F707/PIC16LF707 NOTES: DS41418A-page 114 Preliminary 2010 Microchip Technology Inc. ...
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... T2CKPS<1:0> 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 The TMR2 and PR2 registers are both fully readable and writable. On any Reset, the TMR2 register is set to 00h and the PR2 register is set to FFh. Timer2 is turned on by setting the TMR2ON bit in the T2CON register to a ‘ ...
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... PIC16F707/PIC16LF707 REGISTER 15-1: T2CON: TIMER2 CONTROL REGISTER U-0 R/W-0 R/W-0 — TOUTPS3 TOUTPS2 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS<3:0>: Timer2 Output Postscaler Select bits 0000 = 1:1 Postscaler ...
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... Acquire two samples simultaneously (when using both CSM modules) Two identical implemented on the PIC16F707/PIC16LF707. The modules are named CPSA and CPSB. The timer module integration for both capacitive sensing modules is shown in Table 16-1. A block diagram of the capacitive sensing module is shown in Figure 16-1 and Figure 16-2 ...
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... PIC16F707/PIC16LF707 FIGURE 16-1: CAPACITIVE SENSING BLOCK DIAGRAM CPSxCH<3:0> (1) CPSxON CPSx0 CPSx1 CPSx2 CPSx3 CPSx4 CPSx5 CPSx6 Capacitive CPSx7 Sensing Oscillator CPSx8 CPSxOSC CPSx9 CPSx10 CPSx11 0 Ref- CPSx12 1 DAC CPSx13 CPSx14 Ref+ CPSx15 CPSxRM Watchdog Timer Module LP WDT Overflow WDT OSC Scaler PS< ...
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... FIGURE 16-2: CAPACITIVE SENSING OSCILLATOR BLOCK DIAGRAM CPSx Analog Pin Note 1: Module Enable and Power mode selections are not shown. 2: Comparators remain active in Noise Detection mode. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 Oscillator Module V DD (1) ( (1) ( Internal References 0 0 Ref- Ref+ ...
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... PIC16F707/PIC16LF707 16.1 Analog MUX Each capacitive sensing module can monitor inputs, providing 32 capacitive sensing inputs in total. The capacitive sensing inputs are defined as CPSA<15:0> for capacitive sensing module A, and CPSB<15:0> for capacitive sensing module B. To determine if a frequency change has occurred the use must: • ...
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... Microchip Technology Inc. PIC16F707/PIC16LF707 The remaining mode is a Noise Detection mode that resides within the high range. The Noise Detection mode is unique in that it disables the sinking and sourc- ing of current on the analog pin but leaves the rest of the oscillator circuitry active ...
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... PIC16F707/PIC16LF707 16.6.1 TIMERA/B To select TimerA/B as the timer resource for the capacitive sensing module: • Set the TAXCS/TBXCS bit of the CPSACON0/ CPSBCON0 register. • Clear the TMRACS/TMRBCS bit of the TACON/ TBCON register. When TimerA/B is chosen as the timer resource, the capacitive sensing oscillator will be the clock source for TimerA/B. Refer to Section 14.0 “ ...
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... Sensing” (DS01101) • AN1102, “Layout and Physical Design Guidelines for Capacitive Sensing” (DS01102). 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 16.8 Operation during Sleep The capacitive sensing oscillator will continue to run as long as the module is enabled, independent of the part being in Sleep. In order for the software to determine if a frequency change has occurred, the part must be awake ...
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... PIC16F707/PIC16LF707 REGISTER 16-1: CPSxCON0: CAPACITIVE SENSING CONTROL REGISTER 0 R/W-0/0 R/W-0/0 U-0 CPSxON CPSxRM — bit 7 Legend Readable bit W = Writable bit u = bit is unchanged x = Bit is unknown ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CPSxON: Capacitive Sensing Module Enable bit 1 = Capacitive sensing module is enabled ...
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... Microchip Technology Inc. PIC16F707/PIC16LF707 U-0 R/W-0/0 R/W-0/0 — CPSxCH3 CPSxCH2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
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... PIC16F707/PIC16LF707 TABLE 16-4: SUMMARY OF REGISTERS ASSOCIATED WITH CAPACITIVE SENSING Name Bit 7 Bit 6 Bit 5 ANSELA ANSA7 ANSA6 ANSA5 ANSELB ANSB7 ANSB6 ANSB5 ANSELC ANSC7 ANSC6 ANSC5 ANSELD ANSD7 ANSD6 ANSD5 ANSELE — — — CPSACON0 CPSAON CPSARM — CPSACON1 — — — ...
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... CCP1 pin. Note: CCPRx and CCPx throughout document refer to CCPR1 or CCPR2 and CCP1 or CCP2, respectively. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 TABLE 17-1: CCP MODE – TIMER RESOURCES REQUIRED CCP Mode Capture Compare PWM Note: Timer3 has no connection to either CCP. ...
Page 128
... PIC16F707/PIC16LF707 REGISTER 17-1: CCPxCON: CCPx CONTROL REGISTER U-0 U-0 R/W-0 — — DCxB1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 DCxB<1:0>: PWM Duty Cycle Least Significant bits Capture mode: ...
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... Timer1 is clocked the capture operation may OSC not work. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 17.1.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit of the PIEx register clear to avoid false interrupts ...
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... PIC16F707/PIC16LF707 TABLE 17-3: SUMMARY OF REGISTERS ASSOCIATED WITH CAPTURE Name Bit 7 Bit 6 Bit 5 ANSELB ANSB7 ANSB6 ANSB5 ANSELC ANSC7 ANSC6 ANSC5 APFCON — — — CCP1CON — — DC1B1 CCP2CON — — DC2B1 CCPRxL Capture/Compare/PWM Register X Low Byte CCPRxH Capture/Compare/PWM Register X High Byte ...
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... Clearing the CCPxCON register will force the CCPx compare output latch to the default low level. This is not the PORT I/O data latch. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 17.2.2 TIMER1 MODE SELECTION In Compare mode, Timer1 must be running in either Timer mode or Synchronized Counter mode. The compare operation may not work in Asynchronous Counter mode ...
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... PIC16F707/PIC16LF707 TABLE 17-4: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE Name Bit 7 Bit 6 Bit 5 ADCON0 — — CHS3 ANSELB ANSB7 ANSB6 ANSB5 ANSELC ANSC7 ANSC6 ANSC5 APFCON — — — CCP1CON — — DC1B1 CCP2CON — — DC2B1 CCPRxL Capture/Compare/PWM Register X Low Byte ...
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... In PWM mode, CCPRxH is a read-only register. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 The PWM output (Figure 17-4) has a time base (period) and a time that the output stays high (duty cycle). FIGURE 17-4: Period ...
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... PIC16F707/PIC16LF707 17.3.2 PWM PERIOD The PWM period is specified by the PR2 register of Timer2. The PWM period can be calculated using the formula of Equation 17-1. EQUATION 17-1: PWM PERIOD PWM Period = PR2 + 1 (TMR2 Prescale Value) Note 1/F OSC ...
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... Refer to Section 7.0 “Oscillator Module” for additional details. 17.3.7 EFFECTS OF RESET Any Reset will force all ports to Input mode and the CCP registers to their Reset states. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 EQUATION 17-4: PWM RESOLUTION Resolution = Note: If the pulse width value is greater than the period the assigned PWM pin(s) will remain unchanged ...
Page 136
... PIC16F707/PIC16LF707 TABLE 17-7: SUMMARY OF REGISTERS ASSOCIATED WITH PWM Name Bit 7 Bit 6 Bit 5 ANSELB ANSB7 ANSB6 ANSB5 ANSELC ANSC7 ANSC6 ANSC5 APFCON — — — CCP1CON — — DC1B1 CCP2CON — — DC2B1 CCPRxL Capture/Compare/PWM Register X Low Byte CCPRxH Capture/Compare/PWM Register X High Byte ...
Page 137
... SYNC 1 SPBRG BRGH x 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 The AUSART module includes the following capabilities: • Full-duplex asynchronous transmit and receive • Two-character input buffer • One-character output buffer • Programmable 8-bit or 9-bit character length Synchronous • Address detection in 9-bit mode (AUSART) • ...
Page 138
... PIC16F707/PIC16LF707 FIGURE 18-2: AUSART RECEIVE BLOCK DIAGRAM SPEN RX/DT Pin Buffer and Control Baud Rate Generator + 1 Multiplier SYNC SPBRG BRGH The operation of the AUSART module is controlled through two registers: • Transmit Status and Control (TXSTA) • Receive Status and Control (RCSTA) These registers are detailed in Register 18-1 and Register 18-2, respectively ...
Page 139
... TX/CK I/O pin as an output. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 Note 1: When the SPEN bit is set, the RX/DT I/O pin is automatically configured as an input, regardless of the state of the corresponding TRIS bit and whether or not the AUSART receiver is enabled ...
Page 140
... PIC16F707/PIC16LF707 18.1.1.4 TSR Status The TRMT bit of the TXSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register ...
Page 141
... AUSART receiver. The FIFO and RSR registers are not directly accessible by software. Access to the received data is via the RCREG register. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 Bit 4 Bit 3 Bit 2 Bit 1 INTE ...
Page 142
... PIC16F707/PIC16LF707 18.1.2.2 Receiving Data The receiver data recovery circuit initiates character reception on the falling edge of the first bit. The first bit, also known as the Start bit, is always a zero. The data recovery circuit counts one-half bit time to the center of the Start bit and verifies that the bit is still a zero ...
Page 143
... RCREG register overrun occurred, clear the OERR flag by clearing the CREN receiver enable bit. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 18.1.2.9 9-bit Address Detection Mode Set- up This mode would typically be used in RS-485 systems. To set up an asynchronous reception with address detect enable: 1 ...
Page 144
... PIC16F707/PIC16LF707 FIGURE 18-5: ASYNCHRONOUS RECEPTION Start bit RX/DT pin bit 0 bit 1 Rcv Shift Reg Rcv Buffer Reg Read Rcv Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set ...
Page 145
... TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0 TX9D: Ninth bit of Transmit Data Can be address/data bit or a parity bit. Note 1: SREN/CREN overrides TXEN in Synchronous mode. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 R/W-0 U-0 R/W-0 (1) SYNC — BRGH U = Unimplemented bit, read as ‘0’ ...
Page 146
... PIC16F707/PIC16LF707 REGISTER 18-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 SPEN RX9 SREN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) ...
Page 147
... TX9 TXEN Legend unknown unimplemented read as ‘0’. Shaded cells are not used for the Baud Rate Generator. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 EXAMPLE 18-1: For a device with F 9600, and Asynchronous mode with SYNC = 0 and BRGH = 0 (as seen in Table 18-5): ...
Page 148
... PIC16F707/PIC16LF707 TABLE 18-5: BAUD RATES FOR ASYNCHRONOUS MODES F = 20.000 MHz OSC BAUD SPBRG RATE Actual % Actual value Rate Error (decimal) 300 — — — 1200 1221 1.73 255 2400 2404 0.16 129 9600 9470 -1.36 32 10417 10417 0.00 29 10286 19.2k 19.53k 1 ...
Page 149
... Microchip Technology Inc. PIC16F707/PIC16LF707 SYNC = 0, BRGH = 4.000 MHz F = 3.6864 MHz OSC OSC SPBRG % Actual % value Rate Error Rate Error (decimal) — — — ...
Page 150
... PIC16F707/PIC16LF707 18.3 AUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary cir- cuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry ...
Page 151
... TRISC5 TXREG AUSART Transmit Data Register TXSTA CSRC TX9 TXEN Legend unknown unimplemented read as ‘0’. Shaded cells are not used for synchronous master transmission. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 bit 2 bit 7 bit 0 Word 2 bit 0 bit 2 bit 1 Bit 4 Bit 3 Bit 2 ...
Page 152
... PIC16F707/PIC16LF707 18.3.1.4 Synchronous Master Reception Data is received at the RX/DT pin. The RX/DT pin output driver is automatically disabled when the AUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCSTA register) or the Continuous Receive Enable bit (CREN of the RCSTA register) ...
Page 153
... SREN TRISC TRISC7 TRISC6 TRISC5 TXSTA CSRC TX9 TXEN Legend unknown unimplemented read as ‘0’. Shaded cells are not used for synchronous master reception. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 bit 1 bit 2 bit 3 bit 4 Bit 4 Bit 3 Bit 2 Bit 1 — — ANSC2 ...
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... PIC16F707/PIC16LF707 18.3.2 SYNCHRONOUS SLAVE MODE The following bits are used to configure the AUSART for synchronous slave operation: • SYNC = 1 • CSRC = 0 • SREN = 0 (for transmit); SREN = 1 (for receive) • CREN = 0 (for transmit); CREN = 1 (for receive) • SPEN = 1 Setting the SYNC bit of the TXSTA register configures the device for synchronous operation ...
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... CSRC TX9 TXEN Legend unknown unimplemented read as ‘0’. Shaded cells are not used for synchronous slave reception. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 18.3.2.4 Synchronous Slave Reception Set- up: 1. Set the SYNC and SPEN bits and clear the CSRC bit. ...
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... PIC16F707/PIC16LF707 18.4 AUSART Operation During Sleep The AUSART will remain active during Sleep only in the Synchronous Slave mode. All other modes require the system clock and therefore cannot generate the necessary signals to run the transmit or receive shift registers during Sleep. Synchronous Slave mode uses an externally generated clock to run the transmit and receive shift registers ...
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... LSb MSb General I/O Processor 1 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 A typical SPI connection between microcontroller devices is shown in Figure 19-1. Addressing of more than one slave device is accomplished via multiple hardware slave select lines. External hardware and additional I/O pins must be used to support multiple slave select addressing ...
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... PIC16F707/PIC16LF707 FIGURE 19-2: SPI MODE BLOCK DIAGRAM Read SSPBUF Reg SSPSR Reg SDI bit 0 bit 7 Shift Clock SDO SS Control RA5/SS Enable RA0/SS SSSEL 2 Clock Select Edge Select 2 Edge Select Prescaler SCK 4 TRISx SSPM<3:0> DS41418A-page 158 19.1.1 MASTER MODE In Master mode, data transfer can be initiated at any time because the master controls the SCK line ...
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... In Master mode, all module clocks are halted and the transmission/reception will remain in their current state, paused, until the device wakes from Sleep. After the device wakes up from Sleep, the module will continue to transmit/receive data. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 Preliminary DS41418A-page 159 ...
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... PIC16F707/PIC16LF707 FIGURE 19-3: SPI MASTER MODE WAVEFORM Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO bit 6 bit 7 (CKE = 0) SDO bit 6 bit 7 (CKE = 1) SDI (SMP = 0) bit 7 Input Sample (SMP = 0) SDI (SMP = 1) bit 7 Input Sample (SMP = 1) ...
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... the user to determine which data used and what can be discarded. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 19.1.2.2 Enabling Slave I/O To enable the serial port, the SSPEN bit of the SSPCON register must be set Slave mode of ...
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... PIC16F707/PIC16LF707 FIGURE 19-4: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 SDI (SMP = 0) bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF FIGURE 19-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) ...
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... Flag SSPSR to SSPBUF 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 When the SPI module resets, the bit counter is cleared to ‘0’. This can be done by either forcing the SS pin to a high level or clearing the SSPEN bit. Figure 19-6 shows the timing waveform for such a synchronization event ...
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... PIC16F707/PIC16LF707 REGISTER 19-1: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (SPI MODE) R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in ...
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... UA: Update Address bit 2 Used mode only. bit 0 BF: Buffer Full Status bit 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 R-0 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared Preliminary ...
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... PIC16F707/PIC16LF707 TABLE 19-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION Name Bit 7 Bit 6 Bit 5 ANSELA ANSA7 ANSA6 ANSA5 APFCON — — — INTCON GIE PEIE TMR0IE PIE1 TMR1GIE ADIE RCIE PIR1 TMR1GIF ADIF RCIF PR2 SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register ...
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... SSPSR Reg SDA MSb LSb SSPMSK Reg Match Detect SSPADD Reg Start and Stop bit Detect 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 FIGURE 19-8: Master SDA SCL 2 C The SSP module has six registers for I They are: • SSP Control (SSPCON) register • ...
Page 168
... PIC16F707/PIC16LF707 19.2.2 START AND STOP CONDITIONS During times of no data transfer (Idle time), both the clock line (SCL) and the data line (SDA) are pulled high through external pull-up resistors. The Start and Stop conditions determine the start and stop of data trans- mission ...
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... For a 10-bit address, the first byte would equal ‘1111 0’, where A9 and A8 are the two MSbs of the address. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 The sequence of events for 10-bit address is as follows for reception: 1. Load SSPADD register with high byte of address. ...
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... PIC16F707/PIC16LF707 19.2.5 RECEPTION When the R/W bit of the received address byte is clear, the master will write data to the slave address match occurs, the received address is loaded into the SSPBUF register. An address byte overflow will occur if that loaded address is not read from the SSPBUF before the next complete byte is received ...
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... FIGURE 19-11: I C™ SLAVE MODE TIMING (RECEPTION, 10-BIT ADDRESS) 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 Preliminary DS41418A-page 171 ...
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... PIC16F707/PIC16LF707 19.2.6 TRANSMISSION When the R/W bit of the received address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set and the slave will respond to the master by reading out data. After the address match, an ACK pulse is generated by the slave hardware and the SCL pin is held low (clock is automatically stretched) until the slave is ready to respond ...
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... FIGURE 19-13: I C™ SLAVE MODE TIMING (TRANSMISSION 10-BIT ADDRESS) 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 Preliminary DS41418A-page 173 ...
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... PIC16F707/PIC16LF707 19.2.7 CLOCK STRETCHING During any SCL low phase, any device on the I may hold the SCL line low and delay, or pause, the transmission of data. This “stretching” transmission allows devices to slow down communication on the bus. The SCL line must be constantly sampled by the master to ensure that all devices on the bus have released SCL for more data ...
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... CLOCK SYNCHRONIZATION TIMING SDA DX SCL CKP WR SSPCON 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 19.2.11 SLEEP OPERATION While in Sleep mode, the I addresses of data, and when an address match master complete byte transfer occurs, wake the processor from Sleep (if SSP interrupt is enabled). Master device ...
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... PIC16F707/PIC16LF707 REGISTER 19-3: SSPCON: SYNCHRONOUS SERIAL PORT CONTROL REGISTER (I R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in ...
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... BF: Buffer Full Status bit Receive Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 R-0 R Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared 2 C Standard mode (100 kHz and 1 MHz) ...
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... PIC16F707/PIC16LF707 REGISTER 19-5: SSPMSK: SSP MASK REGISTER R/W-1 R/W-1 R/W-1 MSK7 MSK6 MSK5 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7-1 MSK<7:1>: Mask bits 1 = The received address bit n is compared to SSPADD<n> to detect The received address bit n is not used to detect I bit 0 MSK< ...
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... MOVF PMDATH, W MOVWF HIGHPMBYTE 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 The value written to the PMADRH:PMADRL register pair determines which program memory location is read. The read operation will be initiated by setting the RD bit of the PMCON1 register. The program memory flash controller takes two instructions to complete the read ...
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... PIC16F707/PIC16LF707 REGISTER 20-1: PMCON1: PROGRAM MEMORY CONTROL 1 REGISTER U-1 U-0 U-0 — — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 Unimplemented: Read as ‘1’ bit 6-1 Unimplemented: Read as ‘0’ bit 0 RD: Read Control bit 1 = Initiates a program memory read (The RD is cleared in hardware ...
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... PMDATL Program Memory Read Data Register Low Byte Legend unknown unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used by the program memory read. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 R/W-x R/W-x PMA12 PMA11 U = Unimplemented bit, read as ‘0’ ...
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... PIC16F707/PIC16LF707 NOTES: DS41418A-page 182 Preliminary 2010 Microchip Technology Inc. ...
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... See Section 11.0 “Digital-to-Analog Con- verter (DAC) Module” and Section 10.0 “Fixed Volt- age Reference” for more information on these modules. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 21.1 Wake-up from Sleep The device can wake-up from Sleep through one of the following events: 1 ...
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... PIC16F707/PIC16LF707 21.1.1 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: • If the interrupt occurs before the execution of a SLEEP instruction - SLEEP instruction will execute as a NOP ...
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... For more information on ICSP™ refer to the “PIC16F707/PIC16LF707 Specification” (DS41405A). Note: The ICD 2 produces a V than the maximum V PIC16F707/PIC16LF707. When using this programmer, an external circuit, such as the AC164112 MPLAB age limiter, is required to keep the V voltage within the device specifications 10k ...
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... PIC16F707/PIC16LF707 NOTES: DS41418A-page 186 Preliminary 2010 Microchip Technology Inc. ...
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... INSTRUCTION SET SUMMARY The PIC16F707/PIC16LF707 instruction set is highly orthogonal and is comprised of three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction ...
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... PIC16F707/PIC16LF707 TABLE 23-2: PIC16F707/PIC16LF707 INSTRUCTION SET Mnemonic, Description Operands BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f ANDWF f, d AND W with f CLRF f Clear f CLRW – Clear W COMF f, d Complement f DECF f, d Decrement f DECFSZ f, d Decrement f, Skip if 0 INCF f, d Increment f INCFSZ ...
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... Z Description: AND the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 BCF Syntax: k Operands: Operation: Status Affected: Description: ...
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... PIC16F707/PIC16LF707 BTFSS Bit Test f, Skip if Set Syntax: [ label ] BTFSS f,b 0 f 127 Operands: 0 b < 7 Operation: skip if (f<b> Status Affected: None Description: If bit ‘b’ in register ‘f’ is ‘0’, the next instruction is executed. If bit ‘b’ is ‘1’, then the next ...
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... The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed back in register ‘f’. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 INCFSZ Increment f, Skip if 0 Syntax: [ label ] 0 f 127 Operands: d ...
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... PIC16F707/PIC16LF707 MOVF Move f Syntax: [ label ] MOVF f,d 0 f 127 Operands: d [0,1] (f) (dest) Operation: Status Affected: Z Description: The contents of register f is moved to a destination dependent upon the status destination is W register the destination is file register f itself useful to test a file register since status flag Z is affected ...
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... This is a two-cycle instruction. Words: 1 Cycles: 2 Example: RETFIE After Interrupt PC = TOS GIE = 1 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 RETLW Return with literal in W Syntax: [ label ] 0 k 255 Operands: k (W); Operation: TOS PC Status Affected: None Description: The W register is loaded with the eight bit literal ‘ ...
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... PIC16F707/PIC16LF707 RLF Rotate Left f through Carry Syntax: [ label ] RLF f,d 0 f 127 Operands: d [0,1] Operation: See description below Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘ ...
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... If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is placed in register ‘f’. 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 XORLW Exclusive OR literal with W Syntax: [ label ] XORLW k 0 k 255 Operands: (W) .XOR. k ...
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... PIC16F707/PIC16LF707 NOTES: DS41418A-page 196 Preliminary 2010 Microchip Technology Inc. ...
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... Device Programmers - PICkit™ 2 Programmer - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits 2010 Microchip Technology Inc. PIC16F707/PIC16LF707 24.1 MPLAB Integrated Development Environment Software ® digital signal The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market ...
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... PIC16F707/PIC16LF707 24.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal control- lers. These compilers provide powerful integration capabilities, superior code optimization and ease of use ...
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... Microchip Technology Inc. PIC16F707/PIC16LF707 24.9 MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Micro- chip's most cost effective high-speed hardware ...
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... PIC16F707/PIC16LF707 24.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use inter- face for programming and debugging Microchip’s Flash families of microcontrollers. The ® Windows programming interface supports baseline (PIC10F, PIC12F5xx, ...