PIC16F707-I/MV Microchip Technology, PIC16F707-I/MV Datasheet - Page 175

• Manufacturer Part Number: PIC16F707-I/MV
• Description: 14KB Flash Program, MTouch, 32ch CSM, 1.8V-5.5V, 16MHz Internal Oscillator, 8b A
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ mTouch™ 16Fr

Specifications of PIC16F707-I/MV

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 14KB (8K x 14)
• Program Memory Type: FLASH
• Ram Size: 363 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 14x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-UFQFN Exposed Pad
• Processor Series: PIC16F
• Core: PIC
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

19.2.10
When the CKP bit is cleared, the SCL output is held
low once it is sampled low. Therefore, the CKP bit will
not stretch the SCL line until an external I
device has already asserted the SCL line low. The
SCL output will remain low until the CKP bit is set and
all other devices on the I
This ensures that a write to the CKP bit will not violate
the minimum high time requirement for SCL
(Figure 19-14).
FIGURE 19-14:
 2010 Microchip Technology Inc.
SSPCON
SDA
CKP
SCL
WR
CLOCK SYNCHRONIZATION
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLOCK SYNCHRONIZATION TIMING
2
C bus have released SCL.
DX
2
Master device
asserts clock
C master
Preliminary
PIC16F707/PIC16LF707
19.2.11
While in Sleep mode, the I
addresses of data, and when an address match or
complete byte transfer occurs, wake the processor
from Sleep (if SSP interrupt is enabled).
Master device
deasserts clock
SLEEP OPERATION
2
C module can receive
DS41418A-page 175
DX-1