PIC16LF1519-E/MV Microchip Technology, PIC16LF1519-E/MV Datasheet - Page 231

• Manufacturer Part Number: PIC16LF1519-E/MV
• Description: 40-pin, 28KB Flash, 1024B RAM, 10-bit ADC, 2xCCP, SPI, MI2C, EUSART, 1.8V-3.6V 4
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1519-E/MV

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 28KB (16K x 14)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 28x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: *
• Processor Series: PIC16LF151x
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

21.7
The MSSP module has a Baud Rate Generator avail-
able for clock generation in both I
modes. The Baud Rate Generator (BRG) reload value
is placed in the SSPADD register
When a write occurs to SSPBUF, the Baud Rate Gen-
erator will automatically begin counting down.
Once the given operation is complete, the internal clock
will automatically stop counting and the clock pin will
remain in its last state.
An internal signal “Reload” in
value from SSPADD to be loaded into the BRG counter.
This occurs twice for each oscillation of the module
FIGURE 21-40:
TABLE 21-4:
 2010 Microchip Technology Inc.
Note 1:
Note: Values of 0x00, 0x01 and 0x02 are not valid
BAUD RATE GENERATOR
for SSPADD when used as a Baud Rate
Generator for I
limitation.
16 MHz
16 MHz
16 MHz
4 MHz
The I
100 kHz) in all details, but may be used with care where higher rates are required by the application.
F
OSC
2
C interface does not conform to the 400 kHz I
MSSP CLOCK RATE W/BRG
BAUD RATE GENERATOR BLOCK DIAGRAM
2
C. This is an implementation
SSPM<3:0>
Figure 21-39
SCL
2
C and SPI Master
(Register
4 MHz
4 MHz
4 MHz
1 MHz
SSPM<3:0>
F
triggers the
CY
Control
Reload
21-6).
SSPCLK
Preliminary
Reload
clock line. The logic dictating when the reload signal is
asserted depends on the mode the MSSP is being
operated in.
Table 21-4
instruction cycles and the BRG value loaded into
SSPADD.
EQUATION 21-1:
2
C specification (which applies to rates greater than
BRG Down Counter
PIC16(L)F1516/7/8/9
SSPADD<7:0>
BRG Value
0Ch
09h
27h
09h
F
demonstrates clock rates based on
CLOCK
=
----------------------------------------------

SSPADD
F
OSC
(2 Rollovers of BRG)
/2
F
OSC
400 kHz
DS41452A-page 231
+
308 kHz
100 kHz
100 kHz
F
CLOCK
1
 4  
(1)