PIC16LF1823-I/SL Microchip Technology, PIC16LF1823-I/SL Datasheet - Page 284

• Manufacturer Part Number: PIC16LF1823-I/SL
• Description: 3.5 KB Flash, 128 Bytes RAM, 32 MHz Int. Osc, 12 I/0, Enhanced Mid Range Core, N
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1823-I/SL

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 3.5KB (2K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Processor Series: PIC16LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: MI2C, SPI, EUSART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• On-chip Dac: 5 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC12F/LF1822/PIC16F/LF1823
REGISTER 25-5:
REGISTER 25-6:
DS41413B-page 284
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7-1
bit 0
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
Master mode:
bit 7-0
10-Bit Slave mode — Most Significant Address byte:
bit 7-3
bit 2-1
bit 0
10-Bit Slave mode — Least Significant Address byte:
bit 7-0
7-Bit Slave mode:
bit 7-1
bit 0
R/W-1/1
R/W-0/0
ADD<7:0>: Baud Rate Clock Divider bits
SCL pin clock period = ((ADD<7:0> + 1) *4)/F
Not used: Unused for Most Significant Address byte. Bit state of this register is a “don’t care”. Bit pat-
tern sent by master is fixed by I
compared by hardware and are not affected by the value in this register.
ADD<2:1>: Two Most Significant bits of 10-bit address
Not used: Unused in this mode. Bit state is a “don’t care”.
ADD<7:0>: Eight Least Significant bits of 10-bit address
ADD<7:1>: 7-bit address
Not used: Unused in this mode. Bit state is a “don’t care”.
MSK<7:1>: Mask bits
1 = The received address bit n is compared to SSP1ADD<n> to detect I
0 = The received address bit n is not used to detect I
MSK<0>: Mask bit for I
I
1 = The received address bit 0 is compared to SSP1ADD<0> to detect I
0 = The received address bit 0 is not used to detect I
I
2
2
C Slave mode, 10-bit address (SSP1M<3:0> = 0111 or 1111):
C Slave mode, 7-bit address, the bit is ignored
R/W-0/0
R/W-1/1
SSP1MSK: SSP1 MASK REGISTER
SSP1ADD: MSSP1 ADDRESS AND BAUD RATE REGISTER (I
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
R/W-0/0
R/W-1/1
2
C Slave mode, 10-bit Address
2
C specification and must be equal to ‘11110’. However, those bits are
R/W-1/1
R/W-0/0
Preliminary
ADD<7:0>
MSK<7:0>
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
OSC
R/W-1/1
R/W-0/0
2
2
C address match
C address match
R/W-1/1
R/W-0/0
 2010 Microchip Technology Inc.
2
2
C address match
C address match
R/W-0/0
R/W-1/1
2
C MODE)
R/W-0/0
R/W-1/1
bit 0
bit 0