PIC16LF1827-E/MV Microchip Technology, PIC16LF1827-E/MV Datasheet - Page 142

• Manufacturer Part Number: PIC16LF1827-E/MV
• Description: 7 KB Flash, 384 Bytes RAM, 32 MHz Int. Osc, 16 I/0, Enhanced Mid Range Core, Nan
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1827-E/MV

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-UFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC16F/LF1826/27
15.1.5
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
conversion. The ADC Interrupt Flag is the ADIF bit in
the PIR1 register. The ADC Interrupt Enable is the
ADIE bit in the PIE1 register. The ADIF bit must be
cleared in software.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP instruc-
tion is always executed. If the user is attempting to
wake-up from Sleep and resume in-line code execu-
tion, the GIE and PEIE bits of the INTCON register
must be disabled. If the GIE and PEIE bits of the
INTCON register are enabled, execution will switch to
the Interrupt Service Routine.
Please refer to Section 15.1.5 “Interrupts” for more
information.
FIGURE 15-3:
DS41391C-page 142
Note 1: The ADIF bit is set at the completion of
(ADFM = 0)
(ADFM = 1)
2: The ADC operates during Sleep only
INTERRUPTS
every conversion, regardless of whether
or not the ADC interrupt is enabled.
when the F
10-BIT A/D CONVERSION RESULT FORMAT
MSB
bit 7
bit 7
RC
Unimplemented: Read as ‘0’
oscillator is selected.
ADRESH
10-bit A/D Result
Preliminary
MSB
bit 0
bit 0
15.1.6
The 10-bit A/D conversion result can be supplied in two
formats, left justified or right justified. The ADFM bit of
the ADCON1 register controls the output format.
Figure 15-3 shows the two output formats.
bit 7
bit 7
RESULT FORMATTING
10-bit A/D Result
LSB
Unimplemented: Read as ‘0’
 2010 Microchip Technology Inc.
ADRESL
bit 0
LSB
bit 0