PIC16LF1906T-I/SS Microchip Technology, PIC16LF1906T-I/SS Datasheet - Page 80

• Manufacturer Part Number: PIC16LF1906T-I/SS
• Description: 14KB Flash, 512B RAM, LCD, 11x10b ADC, EUSART, NanoWatt XLP 28 SSOP .209in T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1906T-I/SS

• Processor Series: PIC16LF
• Core: PIC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Data Ram Size: 512 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 1 x 16-bit, 1 x 8-bit
• Operating Supply Voltage: 1.8 V to 5.5 V
• Mounting Style: SMD/SMT
• Package / Case: QFN-28
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: LIN, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 14KB (8K x 14)
• Eeprom Size: -
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Lead Free Status / Rohs Status: Details

PIC16LF1904/6/7
8.1.1
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
FIGURE 8-1:
TABLE 8-1:
DS41569A-page 80
Name
INTCON
IOCBF
IOCBN
IOCBP
PIE1
PIE2
PIR1
PIR2
STATUS
WDTCON
Legend:
Instruction Flow
SLEEP instruction
- SLEEP instruction will execute as a NOP.
- WDT and WDT prescaler will not be cleared
- TO bit of the STATUS register will not be set
- PD bit of the STATUS register will not be
(INTCON reg.)
Note
Interrupt flag
GIE bit
Instruction
Fetched
Instruction
Executed
CLKOUT
cleared.
CLKIN
1:
PC
(1)
(2)
— = unimplemented location, read as ‘0’. Shaded cells are not used in Power-down mode.
WAKE-UP USING INTERRUPTS
GIE = 1 assumed. In this case after wake-up, the processor calls the ISR at 0004h. If GIE = 0, execution will continue in-line.
TMR1GIE
TMR1GIF
IOCBN7
IOCBP7
IOCBF7
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Inst(PC) = Sleep
Bit 7
GIE
—
—
—
—
Inst(PC - 1)
SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
PC
WAKE-UP FROM SLEEP THROUGH INTERRUPT
IOCBF6
IOCBN6
IOCBP6
PEIE
ADIE
ADIF
Bit 6
—
—
—
—
Inst(PC + 1)
Sleep
PC + 1
TMR0IE
IOCBN5
IOCBP5
IOCBF5
RCIE
RCIF
Bit 5
—
—
—
Processor in
Sleep
IOCBN4
IOCBF4
IOCBP4
PC + 2
INTE
TXIE
Bit 4
TXIF
TO
Preliminary
—
—
WDTPS<4:0>
IOCBF3
IOCBN3
IOCBP3
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
IOCIE
Bit 3
Interrupt Latency
Inst(PC + 2)
Inst(PC + 1)
PD
—
—
—
—
• If the interrupt occurs during or after the execu-
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
PC + 2
tion of a SLEEP instruction
- SLEEP instruction will be completely exe-
- Device will immediately wake-up from Sleep
- WDT and WDT prescaler will be cleared
- TO bit of the STATUS register will be set
- PD bit of the STATUS register will be cleared.
cuted
IOCBN2
IOCBP2
TMR0IF
IOCBF2
LCDIE
LCDIF
Bit 2
—
—
Z
(1)
Dummy Cycle
PC + 2
IOCBN1
IOCBF1
IOCBP1
Bit 1
INTF
DC
—
—
—
—
 2011 Microchip Technology Inc.
Dummy Cycle
Inst(0004h)
0004h
SWDTEN
IOCBF0
IOCBN0
IOCBP0
TMR1IE
TMR1IF
IOCIF
Bit 0
—
—
C
Inst(0005h)
Inst(0004h)
Register on
0005h
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