PIC18F13K50T-I/SO Microchip Technology, PIC18F13K50T-I/SO Datasheet - Page 265

• Manufacturer Part Number: PIC18F13K50T-I/SO
• Description: 8 KB Flash, 512 RAM, 15 I/O, 10-bit ADC, USB 2.0 20 SOIC .300in T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F13K50T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: EUSART, I2C, MSSP, SPI, USB
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM164127, DV164126
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 11 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164126 - KIT DEVELOPMENT USB W/PICKIT 2DM164127 - KIT DEVELOPMENT USB 18F14/13K50AC164112 - VOLTAGE LIMITER MPLAB ICD2 VPPXLT20SO1-1 - SOCKET TRANS ICE 20DIP TO 20SOIC
• Lead Free Status / Rohs Status: Details

22.5
The USB module can generate multiple interrupt con-
ditions. To accommodate all of these interrupt sources,
the module is provided with its own interrupt logic
structure, similar to that of the microcontroller. USB
interrupts are enabled with one set of control registers
and trapped with a separate set of flag registers. All
sources are funneled into a single USB interrupt
request, USBIF (PIR2<2>), in the microcontroller’s
interrupt logic.
FIGURE 22-7:
FIGURE 22-8:
 2010 Microchip Technology Inc.
Note
Differential Data
USB Interrupts
1:
The control transfer shown here is only an example showing events that can occur for every transaction. Typical control transfers
will spread across multiple frames.
USB Reset
URSTIF
RESET
UEIR (Flag) and UEIE (Enable) Registers
CRC5EE
CRC5EF
Start-of-Frame (SOF)
BTOEE
BTSEE
BTOEF
BTSEF
Second Level USB Interrupts
PIDEE
PIDEF
CRC16EF
CRC16EE
USB INTERRUPT LOGIC FUNNEL
EXAMPLE OF A USB TRANSACTION AND INTERRUPT EVENTS
DFN8EE
DFN8EF
(USB Error Conditions)
SOFIF
SOF
SETUP
DATA
Preliminary
STATUS
Figure 22-7
module. There are two layers of interrupt registers in
the USB module. The top level consists of overall USB
Status interrupts; these are enabled and flagged in the
UIE and UIR registers, respectively. The second level
consists of USB error conditions, which are enabled
and flagged in the UEIR and UEIE registers. An
interrupt condition in any of these triggers a USB Error
Interrupt Flag (UERRIF) in the top level.
Interrupts may be used to trap routine events in a USB
transaction.
within a USB frame and their corresponding interrupts.
SETUP Token
STALLIE
STALLIF
UERRIE
UERRIF
ACTVIF
ACTVIE
URSTIE
OUT Token
URSTIF
Control Transfer
IDLEIE
From Host
IN Token
IDLEIF
From Host
SOFIE
TRNIE
From Host
SOFIF
TRNIF
UIR (Flag) and UIE (Enable) Registers
Top Level USB Interrupts
PIC18F/LF1XK50
(USB Status Interrupts)
Empty Data
Figure 22-8
Transaction
shows the interrupt logic for the USB
From Host
From Host
To Host
(1)
Data
Data
From Host
shows some common events
To Host
To Host
ACK
ACK
ACK
SOF
1 ms Frame
USBIF
DS41350E-page 265
Set TRNIF
Set TRNIF
Set TRNIF
Transaction
Complete