PIC18F45K20T-I/MV Microchip Technology, PIC18F45K20T-I/MV Datasheet - Page 336

• Manufacturer Part Number: PIC18F45K20T-I/MV
• Description: 32KB, Flash, 1536bytes-RAM, 36I/O, 8-bit Family,nanowatt XLP 40 UQFN 5x5x0.5mm T
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F45K20T-I/MV

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-UFQFN Exposed Pad
• Processor Series: PIC18
• Core: PIC18F
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: I2C, SPI, SCI, USB, MSSP, RJ11
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 35
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MPLAB Integrated Development Environment
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 85 C
• Supply Current (max): 14 uA
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F2XK20/4XK20
GOTO
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
1st word (k<7:0>)
2nd word(k<19:8>)
Description:
Words:
Cycles:
Example:
DS41303G-page 336
Q Cycle Activity:
After Instruction
operation
Decode
PC =
Q1
No
Address (THERE)
Read literal
operation
Unconditional Branch
GOTO k
0  k  1048575
k  PC<20:1>
None
GOTO
anywhere within entire
2-Mbyte memory range. The 20-bit
value ‘k’ is loaded into PC<20:1>.
GOTO
instruction.
2
2
GOTO THERE
‘k’<7:0>,
1110
1111
Q2
No
allows an unconditional branch
is always a two-cycle
k
1111
19
operation
operation
kkk
Q3
No
No
k
kkkk
7
kkk
Read literal
Write to PC
‘k’<19:8>,
operation
Q4
No
kkkk
kkkk
0
8
INCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
Before Instruction
After Instruction
Decode
CNT
Z
C
DC
CNT
Z
C
DC
Q1
=
=
=
=
=
=
=
=
register ‘f’
Increment f
INCF
0  f  255
d  [0,1]
a  [0,1]
(f) + 1  dest
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 24.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
INCF
C, DC, N, OV, Z
Read
0010
Q2
FFh
0
?
?
00h
1
1
1
 2010 Microchip Technology Inc.
f {,d {,a}}
10da
CNT, 1, 0
Process
Data
Q3
ffff
destination
Write to
Q4
ffff