PIC18LF13K22-E/P Microchip Technology, PIC18LF13K22-E/P Datasheet - Page 112

• Manufacturer Part Number: PIC18LF13K22-E/P
• Description: 8KB Flash, 256bytes RAM, 256bytes EEPROM, 16MIPS, NanoWatt XLP 20 PDIP .300in TU
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF13K22-E/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F1XK22/LF1XK22
12.2
Timer3 can be configured for 16-bit reads and writes
(see Figure 12-2). When the RD16 control bit of the
T3CON register is set, the address for TMR3H is
mapped to a buffer register for the high byte of Timer3.
A read from TMR3L will load the contents of the high
byte of Timer3 into the Timer3 High Byte Buffer regis-
ter. This provides the user with the ability to accurately
read all 16 bits of Timer1 without having to determine
whether a read of the high byte, followed by a read of
the low byte, has become invalid due to a rollover
between reads.
A write to the high byte of Timer3 must also take place
through the TMR3H Buffer register. The Timer3 high
byte is updated with the contents of TMR3H when a
write occurs to TMR3L. This allows a user to write all
16 bits to both the high and low bytes of Timer3 at once.
The high byte of Timer3 is not directly readable or
writable in this mode. All reads and writes must take
place through the Timer3 High Byte Buffer register.
Writes to TMR3H do not clear the Timer3 prescaler.
The prescaler is only cleared on writes to TMR3L.
12.3
The Timer1 internal oscillator may be used as the clock
source for Timer3. The Timer1 oscillator is enabled by
setting the T1OSCEN bit of the T1CON register. To use
it as the Timer3 clock source, the TMR3CS bit must
also be set. As previously noted, this also configures
Timer3 to increment on every rising edge of the
oscillator source.
The Timer1 oscillator is described in Section 10.0
“Timer1 Module”.
TABLE 12-1:
DS41365D-page 112
INTCON
IPR2
PIE2
PIR2
TMR3H
TMR3L
TRISA
T1CON
T3CON
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.
Name
Timer3 16-Bit Read/Write Mode
Using the Timer1 Oscillator as the
Timer3 Clock Source
Timer3 Register, High Byte
Timer3 Register, Low Byte
GIE/GIEH PEIE/GIEL TMR0IE
OSCFIP
OSCFIE
OSCFIF
RD16
RD16
Bit 7
—
REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
T1RUN
Bit 6
C1IP
C1IE
C1IF
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC
T3CKPS1 T3CKPS0 T3CCP1
TRISA5
C2IP
C2IE
Bit 5
C2IF
TRISA4
INT0IE
Preliminary
EEIP
EEIE
EEIF
Bit 4
RABIE
BCLIP
BCLIE
BCLIF
Bit 3
12.4
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to FFFFh and overflows to 0000h. The
Timer3 interrupt, if enabled, is generated on overflow
and is latched in interrupt flag bit, TMR3IF of the PIR2
register. This interrupt can be enabled or disabled by
setting or clearing the Timer3 Interrupt Enable bit,
TMR3IE of the PIE2 register.
12.5
If CCP1 module is configured to use Timer3 and to
generate a Special Event Trigger in Compare mode
(CCP1M<3:0>), this signal will reset Timer3. It will also
start an A/D conversion if the A/D module is enabled
(see Section 16.2.8 “Special Event Trigger” for more
information).
The module must be configured as either a timer or
synchronous counter to take advantage of this feature.
When used this way, the CCPR1H:CCPR1L register
pair effectively becomes a period register for Timer3.
If Timer3 is running in Asynchronous Counter mode,
the Reset operation may not work.
In the event that a write to Timer3 coincides with a
Special Event Trigger from a CCP module, the write will
take precedence.
—
Timer3 Interrupt
Resetting Timer3 Using the CCP
Special Event Trigger
T3SYNC
TMR0IF
TRISA2
Bit 2
—
—
—
TMR1CS TMR1ON
TMR3CS TMR3ON
TMR3IP
TMR3IE
TMR3IF
TRISA1
INT0IF
Bit 1
 2010 Microchip Technology Inc.
TRISA0
RABIF
Bit 0
—
—
—
on page
Values
Reset
257
260
260
260
259
259
260
258
259