PIC18LF13K22-E/P Microchip Technology, PIC18LF13K22-E/P Datasheet - Page 51

• Manufacturer Part Number: PIC18LF13K22-E/P
• Description: 8KB Flash, 256bytes RAM, 256bytes EEPROM, 16MIPS, NanoWatt XLP 20 PDIP .300in TU
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF13K22-E/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REGISTER 4-1:
 2010 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
S = Bit can be set by software, but not cleared
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
EEPGD
R/W-x
When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows tracing of the
error condition.
EEPGD: Flash Program or Data EEPROM Memory Select bit
1 = Access Flash program memory
0 = Access data EEPROM memory
CFGS: Flash Program/Data EEPROM or Configuration Select bit
1 = Access Configuration registers
0 = Access Flash program or data EEPROM memory
Unimplemented: Read as ‘0’
FREE: Flash Row (Block) Erase Enable bit
1 = Erase the program memory block addressed by TBLPTR on the next WR command
0 = Perform write-only
WRERR: Flash Program/Data EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal
0 = The write operation completed
WREN: Flash Program/Data EEPROM Write Enable bit
1 = Allows write cycles to Flash program/data EEPROM
0 = Inhibits write cycles to Flash program/data EEPROM
WR: Write Control bit
1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.
0 = Write cycle to the EEPROM is complete
RD: Read Control bit
1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared by hardware. The RD bit can only
0 = Does not initiate an EEPROM read
CFGS
R/W-x
(cleared by completion of erase operation)
operation, or an improper write attempt)
(The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) by software.)
be set (not cleared) by software. RD bit cannot be set when EEPGD = 1 or CFGS = 1.)
EECON1: DATA EEPROM CONTROL 1 REGISTER
W = Writable bit
‘1’ = Bit is set
U-0
—
R/W-0
FREE
Preliminary
PIC18F1XK22/LF1XK22
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
WRERR
R/W-x
(1)
WREN
R/W-0
x = Bit is unknown
R/S-0
WR
DS41365D-page 51
R/S-0
RD
bit 0