PIC18LF14K50T-I/SO Microchip Technology, PIC18LF14K50T-I/SO Datasheet - Page 150

• Manufacturer Part Number: PIC18LF14K50T-I/SO
• Description: 16 KB Flash, 768 RAM, 15 I/O, 10-Bit ADC, USB 2.0, NanoWatt XLP 20 SOIC .300in T
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF14K50T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART, I2C, MSSP, SPI, USB
• Maximum Clock Frequency: 32 KHz
• Number Of Programmable I/os: 18
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM164127, DV164126
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F/LF1XK50
REGISTER 15-4:
DS41350E-page 150
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3-0
WCOL
R/W-0
WCOL: Write Collision Detect bit
In Master Transmit mode:
1 = A write to the SSPBUF register was attempted while the I
0 = No collision
In Slave Transmit mode:
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared by
0 = No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
SSPOV: Receive Overflow Indicator bit
In Receive mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte (must be cleared
0 = No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit mode.
SSPEN: Synchronous Serial Port Enable bit
1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins
0 = Disables serial port and configures these pins as I/O port pins
When enabled, the SDA and SCL pins must be properly configured as inputs.
CKP: SCK Release Control bit
In Slave mode:
1 = Release clock
0 = Holds clock low (clock stretch), used to ensure data setup time
In Master mode:
Unused in this mode.
SSPM<3:0>: Synchronous Serial Port Mode Select bits
1111 = I
1110 = I
1011 = I
1000 = I
0111 = I
0110 = I
Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.
SSPOV
R/W-0
mission to be started (must be cleared by software)
software)
by software)
SSPCON1: MSSP CONTROL 1 REGISTER (I
2
2
2
2
2
2
C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
C Firmware Controlled Master mode (Slave Idle)
C Master mode, clock = F
C Slave mode, 10-bit address
C Slave mode, 7-bit address
W = Writable bit
‘1’ = Bit is set
SSPEN
R/W-0
R/W-0
CKP
Preliminary
OSC
/(4 * (SSPADD + 1))
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SSPM3
R/W-0
2
C MODE)
SSPM2
2
R/W-0
C conditions were not valid for a trans-
 2010 Microchip Technology Inc.
x = Bit is unknown
SSPM1
R/W-0
SSPM0
R/W-0
bit 0