PIC18LF14K50T-I/SO Microchip Technology, PIC18LF14K50T-I/SO Datasheet - Page 51

• Manufacturer Part Number: PIC18LF14K50T-I/SO
• Description: 16 KB Flash, 768 RAM, 15 I/O, 10-Bit ADC, USB 2.0, NanoWatt XLP 20 SOIC .300in T
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18LF14K50T-I/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-SOIC (7.5mm Width)
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART, I2C, MSSP, SPI, USB
• Maximum Clock Frequency: 32 KHz
• Number Of Programmable I/os: 18
• Number Of Timers: 4
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM164127, DV164126
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.0
The Flash program memory is readable, writable and
erasable during normal operation over the entire V
range.
A read from program memory is executed one byte at
a time. A write to program memory is executed on
blocks of 16 or 8 bytes at a time depending on the spe-
cific device (See
erased in blocks of 64 bytes at a time. The difference
between the write and erase block sizes requires from
1 to 8 block writes to restore the contents of a single
block erase. A bulk erase operation can not be issued
from user code.
TABLE 4-1:
Writing or erasing program memory will cease
instruction fetches until the operation is complete. The
program memory cannot be accessed during the write
or erase, therefore, code cannot execute. An internal
programming timer terminates program memory writes
and erases.
A value written to program memory does not need to be
a valid instruction. Executing a program memory
location that forms an invalid instruction results in a
NOP.
FIGURE 4-1:
 2010 Microchip Technology Inc.
PIC18F13K50
PIC18F14K50
Note 1: Table Pointer register points to a byte in program memory.
Device
TBLPTRU
FLASH PROGRAM MEMORY
Table Pointer
WRITE/ERASE BLOCK SIZES
TBLPTRH
Table
TABLE READ OPERATION
Size (bytes)
Write Block
4-1). Program memory is
(1)
16
8
TBLPTRL
Program Memory
(TBLPTR)
Erase Block
Size (bytes)
PIC18F1XK50/PIC18LF1XK50
64
64
Preliminary
DD
Instruction: TBLRD*
Program Memory
4.1
In order to read and write program memory, there are
two operations that allow the processor to move bytes
between the program memory space and the data RAM:
• Table Read (TBLRD)
• Table Write (TBLWT)
The program memory space is 16 bits wide, while the
data RAM space is 8 bits wide. Table reads and table
writes move data between these two memory spaces
through an 8-bit register (TABLAT).
The table read operation retrieves one byte of data
directly from program memory and places it into the
TABLAT register.
table read.
The table write operation stores one byte of data from the
TABLAT register into a write block holding register. The
procedure to write the contents of the holding registers
into program memory is detailed in
to Flash Program
operation of a table write with program memory and data
RAM.
Table operations work with byte entities. Tables contain-
ing data, rather than program instructions, are not
required to be word aligned. Therefore, a table can start
and end at any byte address. If a table write is being
used to write executable code into program memory,
program instructions will need to be word aligned.
Table Reads and Table Writes
Figure 4-1
Memory”.
shows the operation of a
Table Latch (8-bit)
Figure 4-2
Section 4.5 “Writing
TABLAT
DS41350E-page 51
shows the