PIC24FJ32GA104-I/PT Microchip Technology, PIC24FJ32GA104-I/PT Datasheet - Page 167

• Manufacturer Part Number: PIC24FJ32GA104-I/PT
• Description: 16-bit, 16 MIPS, 32KB Flash, 8KB RAM, Nanowatt XLP 44 TQFP 10x10x1mm TRAY
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ32GA104-I/PT

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (11K x 24)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

To set up the SPI module for the Enhanced Buffer
Master mode of operation:
1.
2.
3.
4.
5.
6.
FIGURE 15-2:
 2010 Microchip Technology Inc.
SSx/FSYNCx
If using interrupts:
a)
b)
c)
Write the desired settings to the SPIxCON1
and
(SPIxCON1<5>) = 1.
Clear the SPIROV bit (SPIxSTAT<6>).
Select Enhanced Buffer mode by setting the
SPIBEN bit (SPIxCON2<0>).
Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).
Write the data to be transmitted to the SPIxBUF
register. Transmission (and reception) will start
as soon as data is written to the SPIxBUF
register.
SDOx
SCKx
SDIx
Clear the SPIxIF bit in the respective IFS
register.
Set the SPIxIE bit in the respective IEC
register.
Write the SPIxIP bits in the respective IPC
register.
SPIxCON2
Read SPIxBUF
Control
Sync
Transfer
SPIx MODULE BLOCK DIAGRAM (ENHANCED MODE)
registers
Receive Buffer
8-Level FIFO
bit 0
SPIxSR
with
Control
SPIxBUF
Clock
Shift Control
Transmit Buffer
8-Level FIFO
MSTEN
PIC24FJ64GA104 FAMILY
Transfer
Write SPIxBUF
Select
Edge
To set up the SPI module for the Enhanced Buffer
Slave mode of operation:
1.
2.
3.
4.
5.
6.
7.
8.
16
Clear the SPIxBUF register.
If using interrupts:
a)
b)
c)
Write the desired settings to the SPIxCON1
and
(SPIxCON1<5>) = 0.
Clear the SMP bit.
If the CKE bit is set, then the SSEN bit must be
set, thus enabling the SSx pin.
Clear the SPIROV bit (SPIxSTAT<6>).
Select Enhanced Buffer mode by setting the
SPIBEN bit (SPIxCON2<0>).
Enable SPI operation by setting the SPIEN bit
(SPIxSTAT<15>).
Secondary
1:1 to 1:8
Prescaler
Clear the SPIxIF bit in the respective IFS
register.
Set the SPIxIE bit in the respective IEC
register.
Write the SPIxIP bits in the respective IPC
register to set the interrupt priority.
SPIxCON2
Internal Data Bus
1:1/4/16/64
Prescaler
registers
Primary
DS39951C-page 167
SPIxCON1<1:0>
SPIxCON1<4:2>
Enable
Master Clock
with
F
CY
MSTEN