PIC24FJ32GA104-I/PT Microchip Technology, PIC24FJ32GA104-I/PT Datasheet - Page 50

• Manufacturer Part Number: PIC24FJ32GA104-I/PT
• Description: 16-bit, 16 MIPS, 32KB Flash, 8KB RAM, Nanowatt XLP 44 TQFP 10x10x1mm TRAY
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ32GA104-I/PT

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (11K x 24)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC24FJ64GA104 FAMILY
4.3.3
The upper 32 Kbytes of data space may optionally be
mapped into any 16K word page of the program space.
This provides transparent access of stored constant
data from the data space without the need to use
special instructions (i.e., TBLRDL/H).
Program space access through the data space occurs if
the Most Significant bit (MSb) of the data space EA is ‘1’
and program space visibility is enabled by setting the
PSV bit in the CPU Control register (CORCON<2>). The
location of the program memory space to be mapped
into the data space is determined by the Program Space
Visibility Page Address register (PSVPAG). This 8-bit
register defines any one of 256 possible pages of
16K words in program space. In effect, PSVPAG func-
tions as the upper 8 bits of the program memory
address, with the 15 bits of the EA functioning as the
lower bits. Note that by incrementing the PC by 2 for
each program memory word, the lower 15 bits of data
space addresses directly map to the lower 15 bits in the
corresponding program space addresses.
Data reads to this area add an additional cycle to the
instruction being executed, since two program memory
fetches are required.
Although each data space address, 8000h and higher,
maps directly into a corresponding program memory
address (see Figure 4-7), only the lower 16 bits of the
FIGURE 4-7:
DS39951C-page 50
When CORCON<2> = 1 and EA<15> = 1:
The data in the page
designated by
PSVPAG is mapped
into the upper half of
the data memory
space....
PSVPAG
02
READING DATA FROM PROGRAM
MEMORY USING PROGRAM SPACE
VISIBILITY
PROGRAM SPACE VISIBILITY OPERATION
23
Program Space
15
0
018000h
000000h
010000h
800000h
24-bit program word are used to contain the data. The
upper 8 bits of any program space locations used as
data should be programmed with ‘1111
‘0000 0000’ to force a NOP. This prevents possible
issues should the area of code ever be accidentally
executed.
For operations that use PSV and are executed outside
a REPEAT loop, the MOV and MOV.D instructions will
require one instruction cycle in addition to the specified
execution time. All other instructions will require two
instruction cycles in addition to the specified execution
time.
For operations that use PSV which are executed inside
a REPEAT loop, there will be some instances that
require two instruction cycles in addition to the
specified execution time of the instruction:
• Execution in the first iteration
• Execution in the last iteration
• Execution prior to exiting the loop due to an
• Execution upon re-entering the loop after an
Any other iteration of the REPEAT loop will allow the
instruction accessing data, using PSV, to execute in a
single cycle.
Note:
interrupt
interrupt is serviced
Data Space
PSV Area
PSV access is temporarily disabled during
table reads/writes.
0000h
8000h
FFFFh
 2010 Microchip Technology Inc.
...while the lower
15 bits of the EA
specify an exact
address within the
PSV area. This
corresponds exactly to
the same lower 15 bits
of the actual program
space address.
Data EA<14:0>
1111’ or