PIC24FJ32GA104-I/PT Microchip Technology, PIC24FJ32GA104-I/PT Datasheet - Page 195

• Manufacturer Part Number: PIC24FJ32GA104-I/PT
• Description: 16-bit, 16 MIPS, 32KB Flash, 8KB RAM, Nanowatt XLP 44 TQFP 10x10x1mm TRAY
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ32GA104-I/PT

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (11K x 24)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REGISTER 18-3:
REGISTER 18-4:
 2010 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13-11
bit 10-0
Note 1:
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13-11
bit 10-2
bit 1-0
Note 1:
ADDR7
PTEN7
R/W-0
R/W-0
U-0
U-0
—
—
(1)
(1)
PMA<10:2> bits are not available on 28-pin devices.
PMA<10:2> bits are not available on 28-pin devices.
Unimplemented: Read as ‘0’
CS1: Chip Select 1 bit
1 = Chip Select 1 is active
0 = Chip Select 1 is inactive
Unimplemented: Read as ‘0’
ADDR<10:0>: Parallel Port Destination Address bits
Unimplemented: Read as ‘0’
PTEN14: PMCS1 Strobe Enable bit
1 = PMCS1 functions as chip select
0 = PMCS1 pin functions as port I/O
Unimplemented: Read as ‘0’
PTEN<10:2>: PMP Address Port Enable bits
1 = PMA<10:2> function as PMP address lines
0 = PMA<10:2> function as port I/O
PTEN<1:0>: PMALH/PMALL Strobe Enable bits
1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL
0 = PMA1 and PMA0 pads function as port I/O
ADDR6
PTEN6
PTEN14
R/W-0
R/W-0
R/W-0
R/W-0
CS1
PMADDR: PARALLEL PORT ADDRESS REGISTER
PMAEN: PARALLEL PORT ENABLE REGISTER
(1)
(1)
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
ADDR5
PTEN5
R/W-0
R/W-0
U-0
U-0
—
—
(1)
(1)
ADDR4
PTEN4
R/W-0
R/W-0
U-0
U-0
PIC24FJ64GA104 FAMILY
—
—
(1)
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(1)
ADDR3
PTEN3
R/W-0
R/W-0
U-0
U-0
—
—
(1)
(1)
(1)
ADDR10
PTEN10
ADDR2
PTEN2
R/W-0
R/W-0
R/W-0
R/W-0
(1)
(1)
(1)
(1)
x = Bit is unknown
x = Bit is unknown
ADDR9
ADDR1
PTEN9
PTEN1
R/W-0
R/W-0
R/W-0
R/W-0
(1)
(1)
(1)
DS39951C-page 195
ADDR8
ADDR0
PTEN8
PTEN0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
bit 0
bit 8
bit 0
(1)
(1)
(1)