PIC24FJ64GA102-E/SS Microchip Technology, PIC24FJ64GA102-E/SS Datasheet - Page 70

• Manufacturer Part Number: PIC24FJ64GA102-E/SS
• Description: 16-bit, 16 MIPS, 64KB Flash, 8KB RAM, Nanowatt XLP 28 SSOP .209in TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ64GA102-E/SS

• Processor Series: PIC24
• Core: PIC24F
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 64 KB
• Data Ram Size: 8192 B
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 5
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: SSOP-28
• Development Tools By Supplier: MPLAB Integrated Development Environment
• Minimum Operating Temperature: - 40 C
• Operating Temperature Range: - 40 C to + 125 C
• Supply Current (max): 300 mA
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 21
• Eeprom Size: -
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Lead Free Status / Rohs Status: Details

PIC24FJ64GA104 FAMILY
REGISTER 7-3:
DS39951C-page 70
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14-5
bit 4
bit 3
bit 2
bit 1
bit 0
NSTDIS
R/W-0
U-0
—
NSTDIS: Interrupt Nesting Disable bit
1 = Interrupt nesting is disabled
0 = Interrupt nesting is enabled
Unimplemented: Read as ‘0’
MATHERR: Arithmetic Error Trap Status bit
1 = Overflow trap has occurred
0 = Overflow trap has not occurred
ADDRERR: Address Error Trap Status bit
1 = Address error trap has occurred
0 = Address error trap has not occurred
STKERR: Stack Error Trap Status bit
1 = Stack error trap has occurred
0 = Stack error trap has not occurred
OSCFAIL: Oscillator Failure Trap Status bit
1 = Oscillator failure trap has occurred
0 = Oscillator failure trap has not occurred
Unimplemented: Read as ‘0’
U-0
U-0
—
—
INTCON1: INTERRUPT CONTROL REGISTER 1
W = Writable bit
‘1’ = Bit is set
U-0
U-0
—
—
MATHERR
R/W-0
U-0
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
ADDRERR
R/W-0
U-0
—
STKERR
R/W-0
U-0
—
 2010 Microchip Technology Inc.
x = Bit is unknown
OSCFAIL
R/W-0
U-0
—
U-0
U-0
—
—
bit 8
bit 0