PIC24FV16KA304T-I/MV Microchip Technology, PIC24FV16KA304T-I/MV Datasheet - Page 69

• Manufacturer Part Number: PIC24FV16KA304T-I/MV
• Description: 16KB Flash, 2KB RAM, 512B EEPROM, 16 MIPS, 12-bit ADC, CTMU, 5V 48 UQFN 6x6x0.5m
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FV16KA304T-I/MV

• Processor Series: PIC24FV
• Core: PIC
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 16 KB
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: UQFN-48
• Development Tools By Supplier: MPLAB IDE Software
• Minimum Operating Temperature: - 40 C
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 38
• Eeprom Size: 512 x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Lead Free Status / Rohs Status: Details

6.3
As with Flash program memory, the NVM Address
Registers, NVMADRU and NVMADR, form the 24-bit
Effective Address (EA) of the selected row or word for
data EEPROM operations. The NVMADRU register is
used to hold the upper 8 bits of the EA, while the
NVMADR register is used to hold the lower 16 bits of
the EA. These registers are not mapped into the
Special Function Register (SFR) space; instead, they
directly capture the EA<23:0> of the last table write
instruction that has been executed and selects the data
EEPROM row to erase.
memory EA that is formed for programming and erase
operations.
FIGURE 6-1:
6.4
The EEPROM block is accessed using table read and
write operations similar to those used for program
memory. The TBLWTH and TBLRDH instructions are not
required for data EEPROM operations since the
memory is only 16 bits wide (data on the lower address
is valid only). The following programming operations
can be performed on the data EEPROM:
• Erase one, four or eight words
• Bulk erase the entire data EEPROM
• Write one word
• Read one word
 2011 Microchip Technology Inc.
NVM Address Register
Data EEPROM Operations
DATA EEPROM ADDRESSING WITH TBLPAG AND NVM ADDRESS REGISTERS
Figure 6-1
depicts the program
0
NVMADRU
TBLPAG
7Fh
PIC24FV32KA304 FAMILY
24-Bit PM Address
W Register EA
NVMADR
Like program memory operations, the Least Significant
bit (LSb) of NVMADR is restricted to even addresses.
This is because any given address in the data
EEPROM space consists of only the lower word of the
program memory width; the upper word, including the
uppermost “phantom byte”, are unavailable. This
means that the LSb of a data EEPROM address will
always be ‘0’.
Similarly, the Most Significant bit (MSb) of NVMADRU
is always ‘0’, since all addresses lie in the user program
space.
The library procedures are used in the code examples
detailed in the following sections. General descriptions
of each process are provided for users who are not
using the C30 compiler libraries.
xxxxh
Note 1: Unexpected results will be obtained if the
2: The C30 C compiler includes library
user attempts to read the EEPROM while
a programming or erase operation is
underway.
procedures to automatically perform the
table read and table write operations,
manage the Table Pointer and write
buffers, and unlock and initiate memory
write sequences. This eliminates the
need to create assembler macros or time
critical routines in C for each application.
0
DS39995B-page 69