PIC32MX564F064H-I/MR Microchip Technology, PIC32MX564F064H-I/MR Datasheet - Page 141

• Manufacturer Part Number: PIC32MX564F064H-I/MR
• Description: 64 PINS, 64KB Flash, 32KB RAM, 80 MHz, USB, CAN, 4 DMA 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX564F064H-I/MR

• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN Exposed Pad
• Processor Series: PIC32MX5x
• Core: MIPS32
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 5
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

18.0
© 2010 Microchip Technology Inc.
Note 1: This data sheet summarizes the features
2: Some registers and associated bits
INTER-INTEGRATED CIRCUIT
(I
2
C™)
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 24. “Inter-
Integrated Circuit” (DS61116) in the
“PIC32 Family Reference Manual” , which
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization”
this data sheet for device-specific register
and bit information.
is available from the Microchip web site
(www.microchip.com/PIC32).
in
The I
for both Slave and Multi-Master modes of the I
communication standard.
I
Each I
clock and the SDAx pin is data.
Each I
• I
• I
• I
• I
• Serial clock synchronization for the I
• I
• Provides support for address bit masking
2
PIC32MX5XX/6XX/7XX
C module block diagram.
operation
addressing
master and slaves
be used as a handshake mechanism to suspend
and resume serial transfer (SCLREL control)
collision and arbitrates accordingly
2
2
2
2
2
C interface supporting both master and slave
C Slave mode supports 7-bit and 10-bit addressing
C Master mode supports 7-bit and 10-bit
C port allows bidirectional transfers between
C supports multi-master operation; detects bus
2
C module provides complete hardware support
2
2
C module has a 2-pin interface: the SCLx pin is
C module offers the following key features:
Figure 18-1
DS61156F-page 141
2
C port can
illustrates the
2
C serial