SST38VF6401-90-5I-EKE Microchip Technology, SST38VF6401-90-5I-EKE Datasheet - Page 4

• Manufacturer Part Number: SST38VF6401-90-5I-EKE
• Description: 2.7V To 3.6V 64Mbit Pm Parallel Advanced MPF+ 48 TSOP 12x20 Mm TRAY
• Manufacturer: Microchip Technology

Specifications of SST38VF6401-90-5I-EKE

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 64M (4M x 16)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TFSOP (0.472", 12.0mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Data Sheet
WE# pulse, while the command (50H or 30H) is latched on
the rising edge of the sixth WE# pulse. The internal Erase
operation begins after the sixth WE# pulse. The End-of-
Erase operation can be determined using either Data#
Polling or Toggle Bit methods. The RY/BY# pin can also be
used to monitor the erase operation. For more information,
see Figures 14 and 15 for timing waveforms and Figure 29
for the flowchart.
Any commands, other than Erase-Suspend, issued during
the Sector- or Block-Erase operation are ignored. Any
attempt to Sector- or Block-Erase memory inside a block
protected by Volatile Block Protection, Non-Volatile Block
Protection, or WP# (low) will be ignored. During the com-
mand sequence, WP# should be statically held high or low.
Erase-Suspend/Erase-Resume Commands
The Erase-Suspend operation temporarily suspends a Sec-
tor- or Block-Erase operation thus allowing data to be read
or programmed into any sector or block that is not engaged
in an Erase operation. The operation is executed with a one-
byte command sequence with Erase-Suspend command
(B0H). The device automatically enters read mode within 20
µs (max) after the Erase-Suspend command had been
issued. Valid data can be read, using a Read or Page Read
operation, from any sector or block that is not being erased.
Reading at an address location within Erase-Suspended
sectors or blocks will output DQ
While in Erase-Suspend, a Word-Program or Write-Buffer
Programming operation is allowed anywhere except the
sector or block selected for Erase-Suspend.
To resume a suspended Sector-Erase or Block-Erase oper-
ation, the system must issue the Erase-Resume command.
The operation is executed by issuing one byte command
sequence with Erase-Resume command (30H) at any
address in the last Byte sequence.
When an erase operation is suspended, or re-suspended,
after resume the cumulative time needed for the erase
operation to complete is greater than the erase time of a
non-suspended erase operation. If the hold time from
Erase-Resume to the next Erase- Suspend operation is
less than 200µs, the accumulative erase time can become
very long Therefore, after issuing an Erase-Resume com-
mand, the system must wait at least 200µs before issuing
another Erase-Suspend command. The Erase-Resume
command will be ignored until any program operations initi-
ated during Erase-Suspend are complete.
Bypass mode can be entered while in Erase-Suspend, but
only Bypass Word-Program is available for those sectors or
blocks that are not suspended. Bypass Sector-Erase,
Bypass Block-Erase, and Bypass Chip-Erase, Erase-Sus-
pend, and Erase-Resume are not available. In order to
©2009 Silicon Storage Technology, Inc.
SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404
2
toggling and DQ
64 Mbit (x16) Advanced Multi-Purpose Flash Plus
6
at ‘1’.
4
resume an Erase operation, the Bypass mode must be
exited before issuing Erase-Resume. For more information
about Bypass mode, see “Bypass Mode” on page 7.
Chip-Erase Operation
The SST38VF6401/6402/6403/6404 devices provide a
Chip-Erase operation, which erases the entire memory
array to the ‘1’ state. This operation is useful when the
entire device must be quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command
(10H) at address 555H in the last byte sequence. The
Erase operation begins with the rising edge of the sixth
WE# or CE#, whichever occurs first. During the Erase
operation, the only valid reads are Toggle Bit, Data# Poll-
ing, or RY/BY#. See Table 11 for the command sequence,
Figure 13 for timing diagram, and Figure 29 for the flow-
chart. Any commands issued during the Chip-Erase oper-
ation are ignored. If WP# is low, or any VPBs or NVPBs
are in the protect state, any attempt to execute a Chip-
Erase operation is ignored. During the command
sequence, WP# should be statically held high or low.
Write Operation Status Detection
To
SST38VF6401/6402/6403/6404 provide two software
means to detect the completion of a Write (Program or
Erase) cycle The software detection includes two status
bits: Data# Polling (DQ
Write detection mode is enabled after the rising edge of
WE#, which initiates the internal Program or Erase opera-
tion.
The actual completion of the nonvolatile write is asyn-
chronous with the system. Therefore, Data# Polling or
Toggle Bit maybe be read concurrent with the completion
of the write cycle. If this occurs, the system may possibly
get an incorrect result from the status detection process.
For example, valid data may appear to conflict with either
DQ
failures, the software routine should loop to read the
accessed location an additional two times. If both reads
are valid, then the device has completed the Write cycle,
otherwise the failure is valid.
For the Write-Buffer Programming feature, DQ
the user if either the Write-to-Buffer or Program Buffer-to-
Flash operation aborts. If either operation aborts, then
DQ
to-Buffer Abort Reset command.
7
1
optimize
= 1. DQ
or DQ
6
. To prevent false results, upon detection of
1
must be cleared to '0' by issuing the Write-
the
system
7
) and Toggle Bit (DQ
Write
cycle
S71309-05-000
6
). The End-of-
time,
1
informs
07/09
the