SST38VF6401-90-5I-EKE Microchip Technology, SST38VF6401-90-5I-EKE Datasheet - Page 6

• Manufacturer Part Number: SST38VF6401-90-5I-EKE
• Description: 2.7V To 3.6V 64Mbit Pm Parallel Advanced MPF+ 48 TSOP 12x20 Mm TRAY
• Manufacturer: Microchip Technology

Specifications of SST38VF6401-90-5I-EKE

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 64M (4M x 16)
• Speed: 90ns
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TFSOP (0.472", 12.0mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Data Sheet
Data Protection
The SST38VF6401/6402/6403/6404 provide both hard-
ware and software features to protect nonvolatile data from
inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than
5 ns will not initiate a write cycle.
V
inhibited when V
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Hardware Block Protection
The SST38VF6402 and SST39VF6404 devices support
top hardware block protection, which protects the top boot
block of the device. For SST38VF6402, the boot block con-
sists of the top 32 KWord block, and for SST39VF6404 the
boot block consists of the top two 4 KWord sectors
(8 KWord total).
The SST38VF6401 and SST38VF6403 devices support
bottom hardware block protection, which protects the bot-
tom boot block of the device. For SST38VF6401, the boot
block consists of the bottom 32 KWord block, and for
SST39VF6403 the Boot Block consists of the bottom two 4
KWord sectors (8 KWord total). The boot block addresses
are described in Table 2.
TABLE 2: Boot Block Address Ranges
Program and Erase operations are prevented on the Boot
Block when WP# is low. If WP# is left floating, it is internally
held high via a pull-up resistor. When WP# is high, the Boot
Block is unprotected, which allows Program and Erase
operations on that area.
©2009 Silicon Storage Technology, Inc.
Product
Bottom Boot Uniform
Top Boot Uniform
Bottom Boot Non-Uniform
Top Boot Non-Uniform
DD
SST38VF6401
SST38VF6402
SST38VF6403
SST38VF6404
Power Up/Down Detection: The Write operation is
DD
is less than 1.5V.
32 KW
32 KW
8 KW
8 KW
Size
SST38VF6401 / SST38VF6402 / SST38VF6403 / SST38VF6404
3F8000H-3FFFFFH
3FE000H-3FFFFFH
000000H-007FFFH
000000H-001FFFH
Address Range
64 Mbit (x16) Advanced Multi-Purpose Flash Plus
T2.0 1309
6
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the
device to read array data. When the RST# pin is held low
for at least T
return to Read mode. When no internal Program/Erase
operation is in progress, a minimum period of T
required after RST# is driven high before a valid Read can
take place. See Figure 20 for more information.
The interrupted Erase or Program operation must be re-ini-
tiated after the device resumes normal operation mode to
ensure data integrity.
Software Data Protection (SDP)
The SST38VF6401/6402/6403/6404 devices implement
the JEDEC approved Software Data Protection (SDP)
scheme for all data alteration operations, such as Program
and Erase. These devices are shipped with the Software
Data Protection permanently enabled. See Table 11 for the
specific software command codes.
All Program operations require the inclusion of the three-
byte sequence. The three-byte load sequence is used to
initiate the Program operation, providing optimal protection
from inadvertent Write operations. SDP for Erase opera-
tions is similar to Program, but a six-byte load sequence is
required for Erase operations.
During SDP command sequence, invalid commands will
abort the device to read mode within T
DQ
SDP command sequence.
The SST38VF6401/6402/6403/6404 devices provide
Bypass Mode, which allows for reduced Program and
Erase command sequence lengths. In this mode, the SDP
portion of Program and Erase command sequences are
omitted. See “Bypass Mode” on page 7 for further details.
Common Flash Memory Interface (CFI)
The SST38VF6401/6402/6403/6404 contain Common
Flash Memory Interface (CFI) information that describes
the characteristics of the device. In order to enter the CFI
Query mode, the system can either write a one-byte
sequence using a standard CFI Query Entry command, or
a three-bye sequence using the SST CFI Query Entry
command. A comparison of these two commands is
shown in Table 11. Once the device enters the CFI Query
mode, the system can read CFI data at the addresses
given in Tables 13 through 16.
The system must write the CFI Exit command to return to
Read mode. Note that the CFI Exit command is ignored
during an internal Program or Erase operation. See Table
11 for software command codes, Figures 17 and 18 for
timing waveform, and Figures 27 and 28 for flowcharts.
15
-DQ
8
can be V
RP ,
any in-progress operation will terminate and
IL
or V
IH
, but no other value, during any
RC.
S71309-05-000
The contents of
RHR
07/09
is