XR16V794IV-0B-EVB Exar Corporation, XR16V794IV-0B-EVB Datasheet - Page 15

• Manufacturer Part Number: XR16V794IV-0B-EVB
• Description: Supports V794 64 Ld TQFP,ISA Interface
• Manufacturer: Exar Corporation

Specifications of XR16V794IV-0B-EVB

• Design Resources: XR17V798/794 Eval Board Schematic
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.1
In the event that the receive buffer is overfilling and flow control needs to be executed, the 794 automatically
sends an Xoff message (when enabled) via the serial TX output to the remote modem. The 794 sends the Xoff-
1,2 characters two character times (= time taken to send two characters at the programmed baud rate) after
the receive FIFO crosses the programmed trigger level (for all trigger tables A-D). To clear this condition, the
794 will transmit the programmed Xon-1,2 characters as soon as receive FIFO is less than one trigger level
below the programmed trigger level (for Trigger Tables A, B, and C) or when receive FIFO is less than the
trigger level minus the hysteresis value (for Trigger Table D). This hysteresis value is the same as the Auto
RTS/DTR Hysteresis value in
selected.
* After the trigger level is reached, an xoff character is sent after a short span of time (= time required to send 2 characters);
for example, after 2.083ms has elapsed for 9600 baud and 10-bit word length setting.
A special character detect feature is provided to detect an 8-bit character when bit-5 is set in the Enhanced
Feature Register (EFR). When this character (Xoff2) is detected, it will be placed in the FIFO along with normal
incoming RX data. The 794 compares each incoming receive character with Xoff-2 data. If a match exists, the
received data will be transferred to FIFO and ISR bit-4 will be set to indicate detection of special character.
Although the Internal Register Table shows Xon, Xoff Registers with 8 bits of character information, the actual
number of bits is dependent on the programmed word length. Line Control Register (LCR) bits 0-1 defines the
number of character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. The word length selected by LCR bits 0-1
also determines the number of bits that will be used for the special character comparison. Bit-0 in the Xon, Xoff
Registers corresponds to the LSB bit for the receive character.
The auto RS485 half-duplex direction control changes the behavior of the transmitter when enabled by FCTR
bit-5. It asserts RTS# or DTR# (LOW) after a specified delay indicated in MSR[7:4] following the last stop bit of
the last character that has been transmitted. This helps in turning around the transceiver to receive the remote
station’s response. The delay optimizes the time needed for the last transmission to reach the farthest station
on a long cable network before switching off the line driver. This delay prevents undesirable line signal
disturbance that causes signal degradation. When the host is ready to transmit next polling data packet again,
it only has to load data bytes to the transmit FIFO. The transmitter automatically de-asserts RTS# or DTR#
output (HIGH) prior to sending the data. The auto RS485 half-duplex direction control also changes the
transmitter empty interrupt to TSR empty instead of THR empty.
Each UART in the 794 includes the infrared encoder and decoder compatible to the IrDA (Infrared Data
Association) version 1.0. The input pin ENIR conveniently activates all 4 UART channels to start up in the
infrared mode. Note that the ENIR pin is sampled when the RST# input is de-asserted. This global control pin
enables the MCR bit-6 function in every UART channel register. After power up or a reset, the software can
overwrite MCR bit-6 if so desired. ENIR and MCR bit-6 also disable the receiver while the transmitter is
sending data. This prevents echoed data from reaching the receiver. The global activation ENIR pin prevents
the infrared emitter from turning on and drawing large amount of current while the system is starting up. When
the infrared feature is enabled, the transmit data outputs, TX[7:0], would idle at logic zero level. Likewise, the
RX [7:0] inputs assume an idle level of logic zero.
2.12
2.13
2.14
RX T
Infrared Mode
RIGGER
Special Character Detect
Auto RS485 Half-duplex Control
16
24
28
8
L
EVEL
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
INT P
T
ABLE
IN
Table 17
A
16
24
28
8
CTIVATION
6: A
UTO
.
Table 6
X
ON
X
/X
(
OFF
CHARACTERS IN RX FIFO
OFF
below explains this when Trigger Table-B (See
C
15
(S
HARACTER
OFTWARE
16*
24*
28*
8*
(
S
) S
) F
ENT
LOW
)
C
ONTROL
X
(
CHARACTERS IN RX FIFO
ON
C
HARACTER
16
24
0
8
XR16V794
(
S
) S
Table 14
ENT
)
) is