XR16V794IV-0B-EVB Exar Corporation, XR16V794IV-0B-EVB Datasheet - Page 20

• Manufacturer Part Number: XR16V794IV-0B-EVB
• Description: Supports V794 64 Ld TQFP,ISA Interface
• Manufacturer: Exar Corporation

Specifications of XR16V794IV-0B-EVB

• Design Resources: XR17V798/794 Eval Board Schematic
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

A
XR16V794
HIGH PERFORMANCE 2.25V TO 3.6V QUAD UART WITH FRACTIONAL BAUD RATE
[A7:A0]
The XR16V794 has a global interrupt source register set that consists of 4 consecutive registers [INT0, INT1,
INT2 and INT3]. The four registers are in the device configuration register address space.
All four registers default to logic zero (as indicated in square braces) for no interrupt pending. All 4 channel
interrupts are enabled or disabled in each channel’s IER register. INT0 shows individual status for each
channel while INT1, INT2 and INT3 show the details of the source of each channel’s interrupt with its unique 3-
bit encoding.
wake-up interrupts are masked in the device configuration registers,
generated (if enabled) by the 794 when awakened from sleep if all 4 channels were placed in the sleep mode
previously.
Each bit gives an indication of the channel that has requested for service. For example, bit-0 represents
channel 0 and bit-3 indicates channel 3. Logic one indicates the channel N [3:0] has called for service. Bits 4 to
7 are reserved and remains at logic zero. The interrupt bit clears after reading the appropriate register of the
interrupting UART channel register (ISR, LSR and MSR).
interrupt clearing details.
DDRESS
0x8A
0x8B
0x8C
0x8D
0x8E
0x80
0x81
0x82
0x83
0x84
0x85
0x86
0x87
0x88
0x89
3.1.1
R
W
R/W
R/W
R/W TIMER MSB
R/W
R/W
R/W
The Global Interrupt Source Registers
EAD
RITE
W
R
R
R
R
R
R
R
R
/
Figure 13
TIMER LSB
INT Source Reserved Reserved Reserved Reserved
8X MODE
R
RESET
SLEEP
TIMER
TIMER
REGA
REGB
EGISTER
DREV
CTRL
INT 1
INT 2
INT 3
DVID
shows the 4 interrupt registers in sequence for clarity. The 16-bit timer and sleep
Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved
UART 2
UART 7
Bit 7
bit 1
bit 7
bit 7
bit 7
[0x00]
0
0
0
0
0
T
INT3
ABLE
8: D
UART 6
source
Bit 6
bit 0
bit 6
bit 6
bit 6
0
0
0
1
0
EVICE
[0x00]
INT2
C
UART 1
UART 5
ONFIGURATION
Bit 5
bit 2
bit 5
bit 5
bit 5
0
0
0
0
0
20
SEE ”INTERRUPT CLEARING:” ON PAGE 30.
[0x00]
INT1
interrupt
UART 4
Bit 4
bit 1
bit 4
bit 4
bit 4
0
0
0
0
0
R
EGISTERS
TIMERCNTL and SLEEP.
UART 3
UART 3
UART 3
UART 3
UART 3
Enable
source
source
[0x00]
Reset
clock
sleep
INT0
Bit 3
bit 0
bit 2
bit 3
bit 3
bit 3
0
0
0
0
interrupt
UART 2
UART 0
function
UART 2
UART 2
UART 2
Enable
select
Reset
sleep
Bit 2
bit 2
bit 1
bit 2
bit 2
bit 2
0
0
1
0
start timer
interrupt
UART 1
UART 1
UART 1
UART 1
Enable
source
Reset
sleep
Bit 1
bit 1
bit 0
bit 1
bit 1
bit 1
0
0
0
0
An interrupt is
REV. 1.0.1
write to all
timer INT
UART 0
UART 2
UART 0
UART 0
UART 0
Enable
UARTs
source
enable
Reset
sleep
Bit 0
bit 0
bit 2
bit 0
bit 0
bit 0
0
0
0
for