LMF90CIN National Semiconductor, LMF90CIN Datasheet - Page 14

• Manufacturer Part Number: LMF90CIN
• Manufacturer: National Semiconductor

Specifications of LMF90CIN

• Architecture: Switched Capacitor
• Single Supply Voltage (typ): 5V
• Dual Supply Voltage (typ): ±3/±5V
• Power Supply Requirement: Single/Dual
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Package Type: MDIP
• Lead Free Status / RoHS Status: Not Compliant

2 0 Applications Information
NOISE
Switched-capacitor filters have two kinds of noise at their
outputs There is a random ‘‘thermal’’ noise component
whose level is typically on the order of hundreds of micro-
volts The other kind of noise is digital clock feedthrough
This will have an amplitude in the vicinity of 50 mV peak-to-
peak In some applications the clock noise frequency is so
high compared to the signal frequency that it is unimportant
In other cases clock noise may have to be removed from
the output signal with for example a passive low-pass filter
at the LMF90’s output pin
CLOCK FREQUENCY LIMITATIONS
The performance characteristics of a switched-capacitor fil-
ter depend on the switching (clock) frequency At very low
clock frequencies (below 10 Hz) the time between clock
cycles is relatively long and small parasitic leakage currents
cause the internal capacitors to discharge sufficiently to af-
fect the filter’s offset voltage and gain This effect becomes
more pronounced at elevated operating temperatures
At higher clock frequencies performance deviations are pri-
marily due to the reduced time available for the internal op-
erational amplifiers to settle Best performance with high
clock frequencies will be obtained when the filter clock’s
duty cycle is 50% The clock frequency divider when used
provides a 50% duty cycle clock to the filter but when an
external clock is applied to CLK it should have a duty cycle
close to 50% for best performance
Input Impedance
The input to the bandpass section of the LMF90 (V
similar to the switched-capacitor circuit shown in Figure 5
During the first half of a clock cycle the
charging C
half-cycle the
transferred to the feedback capacitor At frequencies well
below the clock frequency the input impedance approxi-
mates a resistor whose value is
At the bandpass filter input C
worst-case calculation of effective R
3 0 pF and f
IN
CLK
R
to the input voltage V
IN
2
(Min)
e
switch closes and the charge on C
1 5 MHz Thus
R
e
IN
4 5 x 10
e
C
1
IN
IN
1
f
b
is nominally 3 0 pF For a
CLK
6
e
IN
IN
222 k
During the second
assume C
1
switch closes
(Continued)
IN1
IN
IN
) is
e
is
14
At the maximum clock frequency of 1 5 MHz the lowest
typical value for the effective R
fore 222 k
the input impedance will be greater than or equal to this
value Source impedance should be low enough that this
input impedance doesn’t significantly affect gain
The summing amplifier input impedance at V
ed in a similar manner except that C
a minimum input impedance of 133 k
inputs are connected together the combined input imped-
ance will be 83 3 k
2 5 POWER SUPPLY AND CLOCK OPTIONS
The LMF90 is designed to operate from either single or dual
power supply voltages from 5V to 15V In either case the
supply pins should be well-bypassed to minimize any feed-
through of power supply noise into the filter’s signal path
Such feedthrough can significantly reduce the depth of the
notch For operation from dual supply voltages connect V
(pin 8) to the negative supply GND (pin 13) to the system
ground and V
For single supply operation simply connect V
ground and GND (Pin 13) to a ‘‘clean’’ reference voltage at
mid-supply This reference voltage can be developed with a
pair of resistors and a capacitor as shown in Figures 10
through 16 Note that for single supply operation the three-
level logic inputs should be connected to system ground
and V
ate properly with TTL-level clock signals when the LMF90 is
powered from either single or dual supplies because it has
two TTL thresholds one referred to the V
referred to the GND pin XLS should be connected to the
V
through 16 illustrate a wide variety of power supply and
clock options
stage At frequencies well below the center frequency
b
FIGURE 5 Simplified LMF90 bandpass section input
pin when an external TTL clock is used Figures 6
a
the input impedance appears to be resistive
2 instead of V
Note that R
a
to the positive supply
with a 1 5 MHz filter clock
b
IN
and GND The CLK input will oper-
increases as f
IN
at the V
IN
e
at V
CLK
5 0 pF This yields
IN1
IN2
b
IN2
decreases so
input is there-
b
pin and one
When both
TL H 10354 – 9
is calculat-
to system
b