DS90CF364AMTDX National Semiconductor, DS90CF364AMTDX Datasheet
DS90CF364AMTDX
Specifications of DS90CF364AMTDX
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DS90CF364AMTDX Summary of contents
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... This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces. Block Diagrams DS90CF384A Order Number DS90CF384AMTD See NS Package Number MTD56 TRI-STATE® registered trademark of National Semiconductor Corporation. © 2011 National Semiconductor Corporation DS90CF384A/DS90CF364A Features ■ MHz shift clock support ■ ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( CMOS/TTL Input Voltage CMOS/TTL Output Voltage LVDS Receiver Input Voltage Junction Temperature Storage Temperature Lead Temperature (Soldering, 4 sec) Solder Reflow Temperature ...
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Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions ...
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AC Timing Diagrams FIGURE 2. “16 Grayscale” Test Pattern www.national.com FIGURE 1. “Worst Case” Test Pattern (DS90CF384A)(Note 4 10087002 10087012 5, Note 6, Note 7, Note 8) ...
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FIGURE 3. “16 Grayscale” Test Pattern Note 5: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. Note 6: The 16 grayscale test pattern tests device power consumption for a “typical” LCD ...
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FIGURE 5. DS90CF384A/DS90CF364A (Receiver) Setup/Hold and High/Low Times FIGURE 6. DS90CF384A/DS90CF364A (Receiver) Clock In to Clock Out Delay FIGURE 7. DS90CF384A/DS90CF364A (Receiver) Phase Lock Loop Set Time www.national.com 10087005 10087006 6 10087007 ...
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FIGURE 8. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CF384A FIGURE 9. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs - DS90CF364A FIGURE 10. DS90CF384A/DS90CF364A (Receiver) Power Down Delay 10087008 7 10087009 10087010 www.national.com ...
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FIGURE 11. DS90CF384A (Receiver) LVDS Input Strobe Position www.national.com 8 10087025 ...
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FIGURE 12. DS90CF364A (Receiver) LVDS Input Strobe Position 9 10087026 www.national.com ...
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C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max Tppos—Transmitter output pulse position (min and max) RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) + ISI ...
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DS90CF384A Pin Descriptions — 56L TSSOP Package — 24-Bit FPD Link Receiver Pin Name I/O No. RxIN Positive LVDS differentiaI data inputs. RxIN− Negative LVDS differential data inputs. RxOUT O 28 TTL level data outputs. This ...
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Pin Diagram for TSSOP Packages DS90CF384A www.national.com 10087023 12 DS90CF364A 10087013 ...
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Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Molded Thin Shrink Small Outline Package, JEDEC 48-Lead Molded Thin Shrink Small Outline Package, JEDEC Dimensions shown in millimeters only Order Number DS90CF384AMTD NS Package Number MTD56 Dimensions shown in millimeters only ...
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... For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Amplifiers www.national.com/amplifiers Audio www.national.com/audio Clock and Timing www.national.com/timing Data Converters www.national.com/adc Interface www.national.com/interface LVDS www.national.com/lvds Power Management www.national.com/power Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www ...