LTC3731HGTR Linear Technology, LTC3731HGTR Datasheet - Page 11

• Manufacturer Part Number: LTC3731HGTR
• Manufacturer: Linear Technology

Specifications of LTC3731HGTR

• Lead Free Status / RoHS Status: Not Compliant

OPERATIO
C) Continuous Current Operation
Tying the FCB pin to ground will force continuous current
operation. This is the least efficient operating mode, but
may be desirable in certain applications. The output can
source or sink current in this mode. When sinking current
while in forced continuous operation, the controller will
cause current to flow back into the input filter capacitor.
If large enough, the input capacitor will prevent the input
supply from boosting to unacceptably high levels; see C
C
Frequency Synchronization
The phase-locked loop allows the internal oscillator to be
synchronized to an external source using the PLLIN pin.
The output of the phase detector at the PLLFLTR pin is also
the DC frequency control input of the oscillator, which
operates over a 250kHz to 600kHz range corresponding to
a voltage input from 0V to 2.4V. When locked, the PLL
aligns the turn on of the top MOSFET to the rising edge of
the synchronizing signal. When no frequency information
is supplied to the PLLIN pin, PLLFLTR goes low, forcing the
oscillator to minimum frequency. A DC source can be
applied to the PLLFLTR pin to externally set the desired
operating frequency. A discharge current of approximately
20µA will be present at the pin with no PLLIN input signal.
Input capacitance ESR requirements and efficiency losses
are reduced substantially in a multiphase architecture
because the peak current drawn from the input capacitor
is effectively divided by the number of phases used and
power loss is proportional to the RMS current squared. A
3-stage, single output voltage implementation can reduce
input path power loss by 90%.
Power Good
The PGOOD pin is connected to the drain of an internal
N-channel MOSFET. The MOSFET is turned on once an
internal delay of about 100µs has elapsed and the output
voltage has been away from its nominal value by greater than
10%. If the output returns to normal prior to the delay
timeout, the timer is reset. There is no delay time for the
rising of the PGOOD output once the output voltage is within
the ±10% “window.”
OUT
selection in the Applications Information section.
U
(Refer to Functional Diagram)
IN
/
Phase Mode
The PHASMD pin determines the phase shift between the
rising edge of the TG1 output and the rising edge of the
CLKOUT signal. Grounding the pin will result in 30 degrees
phase shift and tying the pin to V
degrees. These phase shift values enable extension to 6-
and 12-phase systems. The PGOOD function above and
the PHASMD function are tied to a common pin in the UH
package.
Undervoltage Shutdown Adjust
The voltage applied to the UVADJ pin is compared to the
internal 1.2V reference to have an externally program-
mable undervoltage shutdown. The RUN/SS pin is inter-
nally held low until the voltage applied to the UVADJ pin
exceeds the 1.2V threshold.
Short-Circuit Detection
The RUN/SS capacitor is used initially to turn on and limit
the inrush current from the input power source. Once the
controllers have been given time, as determined by the
capacitor on the RUN/SS pin, to charge up the output
capacitors and provide full load current, the RUN/SS
capacitor is then used as a short-circuit timeout circuit. If
the output voltage falls to less than 70% of its nominal
output voltage, the RUN/SS capacitor begins discharg-
ing, assuming that the output is in a severe overcurrent
and/or short-circuit condition. If the condition lasts for a
long enough period, as determined by the size of the
RUN/SS capacitor, the controller will be shut down until
the RUN/SS pin voltage is recycled. This built-in latchoff
can be overridden by providing >5µA at a compliance of
3.8V to the RUN/SS pin. This additional current shortens
the soft-start period but prevents net discharge of the
RUN/SS capacitor during a severe overcurrent and/or
short-circuit condition. Foldback current limiting is acti-
vated when the output voltage falls below 70% of its
nominal level whether or not the short-circuit latchoff
circuit is enabled. Foldback current limit can be overrid-
den by clamping the EAIN pin such that the voltage is held
above the (70%)(0.6V) or 0.42V level even when the
actual output voltage is low. Up to 100µA of input current
can safely be accommodated by the RUN/SS pin.
CC
LTC3731H
will result in 60
11
3731hfa