LTC3731HGTR Linear Technology, LTC3731HGTR Datasheet - Page 14

• Manufacturer Part Number: LTC3731HGTR
• Manufacturer: Linear Technology

Specifications of LTC3731HGTR

• Lead Free Status / RoHS Status: Not Compliant

APPLICATIO S I FOR ATIO
LTC3731H
in applications that have an output voltage that is less than
1/3 of the input voltage. In applications where V
the top MOSFETs’ “on” resistance is normally less impor-
tant for overall efficiency than its input capacitance at
operating frequencies above 300kHz. MOSFET manufac-
turers have designed special purpose devices that provide
reasonably low “on” resistance with significantly reduced
input capacitance for the main switch application in switch-
ing regulators.
The peak-to-peak MOSFET gate drive levels are set by the
voltage, V
MOSFETs in most applications. Pay close attention to the
BV
logic-level MOSFETs are limited to 30V or less.
Selection criteria for the power MOSFETs include the “on”
resistance R
maximum output current.
MOSFET input capacitance is a combination of several
components but can be taken from the typical “gate
charge” curve included on most data sheets (Figure 5).
The curve is generated by forcing a constant input current
into the gate of a common source, current source loaded
stage and then plotting the gate voltage versus time. The
initial slope is the effect of the gate-to-source and the gate-
to-drain capacitance. The flat portion of the curve is the
result of the Miller multiplication effect of the drain-to-gate
capacitance as the drain drops the voltage across the
current source load. The upper sloping line is due to the
drain-to-gate accumulation capacitance and the gate-to-
source capacitance. The Miller charge (the increase in
coulombs on the horizontal axis from a to b while the curve
is flat) is specified for a given V
adjusted for different V
14
DSS
V
GS
specification for the MOSFETs as well; many of the
CC
C
MILLER
DS(ON)
Figure 5. Gate Charge Characteristic
, requiring the use of logic-level threshold
a
MILLER EFFECT
= (Q
Q
IN
B
, input capacitance, input voltage and
U
– Q
A
)/V
b
DS
DS
U
voltages by multiplying by the
DS
drain voltage, but can be
W
V
+
GS
–
V
IN
+
U
–
3731H F05
V
>> V
DS
V
IN
OUT
,
ratio of the application V
values. A way to estimate the C
change in gate charge from points a and b on a manufac-
turers data sheet and divide by the stated V
specified. C
for determining the transition loss term in the top MOSFET
but is not directly specified on MOSFET data sheets. C
and C
parameters are not included.
When the controller is operating in continuous mode the
duty cycles for the top and bottom MOSFETs are given by:
The power dissipation for the main and synchronous
MOSFETs at maximum output current are given by:
where N is the number of output stages, δ is the tempera-
ture dependency of R
resistance (approximately 2Ω at V
drain potential and the change in drain potential in the
particular application. V
typical gate threshold voltage specified in the power
MOSFET data sheet at the specified drain current. C
is the calculated capacitance using the gate charge curve
from the MOSFET data sheet and the technique described
above.
P
Main Switch Duty Cycle
Synchronous Switch Duty Cycle
P
SYNC
MAIN
OS
are specified sometimes but definitions of these
=
=
MILLER
V
V
V
⎡
⎢
⎣
V
IN
IN
OUT
V
IN
CC
2
–
V
I
IN
MAX
2
–
V
⎛
⎜
⎝
is the most important selection criteria
N
OUT
I
1
V
MAX
DS(ON)
N
TH IL
(
R
( )
⎛
⎜
⎝
TH(IL)
⎞
⎟
⎠
DR
I
MAX
2
DS
N
(
)(
, R
+
1
=
C
+
to the curve specified V
V
DR
⎞
⎟
⎠
is the data sheet specified
V
MILLER
TH IL
δ
MILLER
2
V
OUT
1
(
IN
)
is the effective top driver
( )
1
R
GS
+
DS ON
= V
⎤
⎥
⎦
δ
=
)
(
( )
)
term is to take the
f
•
⎛
⎜
⎝
R
MILLER
V
)
DS ON
IN
+
(
–
V
IN
DS
), V
V
)
OUT
IN
voltage
MILLER
is the
⎞
⎟
⎠
3731hfa
RSS
DS