LTC3731HGTR Linear Technology, LTC3731HGTR Datasheet - Page 15

• Manufacturer Part Number: LTC3731HGTR
• Manufacturer: Linear Technology

Specifications of LTC3731HGTR

• Lead Free Status / RoHS Status: Not Compliant

APPLICATIO S I FOR ATIO
Both MOSFETs have I
equation includes an additional term for transition losses,
which peak at the highest input voltage. For V
high current efficiency generally improves with larger
MOSFETs, while for V
rapidly increase to the point that the use of a higher
R
efficiency. The synchronous MOSFET losses are greatest
at high input voltage when the top switch duty factor is low
or during a short circuit when the synchronous switch is
on close to 100% of the period.
The term (1 + δ ) is generally given for a MOSFET in the
form of a normalized R
δ = 0.005/°C can be used as an approximation for low
voltage MOSFETs.
The Schottky diodes (D1 to D3 in Figure 1) conduct during
the dead time between the conduction of the two large
power MOSFETs. This prevents the body diode of the
bottom MOSFET from turning on, storing charge during
the dead time and requiring a reverse recovery period
which could cost as much as several percent in efficiency.
A 2A to 8A Schottky is generally a good compromise for
both regions of operation due to the relatively small
average current. Larger diodes result in additional transi-
tion loss due to their larger junction capacitance.
C
In continuous mode, the source current of each top
N-channel MOSFET is a square wave of duty cycle V
A low ESR input capacitor sized for the maximum RMS
current must be used. The details of a close form equation
can be found in Application Note 77. Figure 6 shows the
input capacitor ripple current for different phase configu-
rations with the output voltage fixed and input voltage
varied. The input ripple current is normalized against the
DC output current. The graph can be used in place of
tedious calculations. The minimum input ripple current
can be achieved when the product of phase number and
output voltage, N(V
input voltage V
IN
DS(ON)
and C
device with lower C
OUT
Selection
IN
or:
U
OUT
2
R losses while the topside N-channel
DS(ON)
IN
), is approximately equal to the
U
MILLER
> 12V, the transition losses
vs temperature curve, but
actually provides higher
W
IN
U
< 12V, the
OUT
/V
IN
.
So the phase number can be chosen to minimize the input
capacitor size for the given input and output voltages.
In the graph of Figure 4, the local maximum input RMS
capacitor currents are reached when:
These worst-case conditions are commonly used for de-
sign because even significant deviations do not offer much
relief. Note that capacitor manufacturer’s ripple current
ratings are often based on only 2000 hours of life. This
makes it advisable to further derate the capacitor or to
choose a capacitor rated at a higher temperature than re-
quired. Several capacitors may also be paralleled to meet
size or height requirements in the design. Always consult
the capacitor manufacturer if there is any question.
The Figure 6 graph shows that the peak RMS input current
is reduced linearly, inversely proportional to the number N
of stages used. It is important to note that the efficiency
loss is proportional to the input RMS current squared and
therefore a 3-stage implementation results in 90% less
V
V
V
V
OUT
OUT
IN
IN
Figure 6. Normalized Input RMS Ripple Current
vs Duty Factor for One to Six Output Stages
=
=
0.6
0.5
0.4
0.3
0.2
0.1
0
N
2
k
0.1
k
N
–
where k
0.2
1
where k
0.3
DUTY FACTOR (V
0.4
= 1 2
1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE
12-PHASE
0.5
, , ..., –
=
1 2
OUT
0.6
, , ...,
/V
N
IN
0.7
)
1
0.8
LTC3731H
N
3731H F06
0.9
15
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