CY7C4251-10JC Cypress Semiconductor Corp, CY7C4251-10JC Datasheet - Page 7

• Manufacturer Part Number: CY7C4251-10JC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4251-10JC

• Configuration: Dual
• Density: 64Kb
• Access Time (max): 8ns
• Word Size: 9b
• Organization: 8Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 35mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 32
• Lead Free Status / RoHS Status: Not Compliant

Programmable Flag (PAE, PAF) Operation
Whether the flag offset registers are programmed as described
in
almost-empty flag (PAE) and programmable almost-full flag
(PAF) states are determined by their corresponding offset
registers and the difference between the read and write pointers.
The number formed by the empty offset least significant bit
register and empty offset most significant register is referred to
as n and determines the operation of PAE. PAE is synchronized
to the LOW-to-HIGH transition of RCLK by one flip-flop and is
LOW when the FIFO contains n or fewer unread words. PAE is
set HIGH by the LOW-to-HIGH transition of RCLK when the
FIFO contains (n + 1) or greater unread words.
The number formed by the full offset least significant bit register
and full offset most significant bit register is referred to as m and
determines the operation of PAF. PAE is synchronized to the
LOW-to-HIGH transition of WCLK by one flip-flop and is set LOW
when the number of unread words in the FIFO is greater than or
equal to CY7C4421. (64 – m), CY7C4201 (256 – m), CY7C4211
Table 3. Status Flags
Document #: 38-06016 Rev. *D
0
1 to n
(n + 1) to 32
33 to (64 – (m + 1))
(64 – m)
64
0
1 to n
(n + 1) to 512
513 to (1024 – (m + 1))
(1024 – m)
1024
Notes
1. The same selection sequence applies to reading from the registers. REN1 and REN2 are enabled and a read is performed on the LOW-to-HIGH transition of RCLK.
2. n = Empty Offset (n = 7 default value).
3. m = Full Offset (m = 7 default value).
Table 2
[2]
[2]
CY7C4221
CY7C4421
[3]
or the default values are used, the programmable
[3]
to 63
to 1023
0
1 to n
(n + 1) to 1024
1025 to (2048 – (m + 1)) 2049 to (4096 – (m + 1)) 4097 to (8192 – (m + 1))
(2048 – m)
2048
0
1 to n
(n + 1) to 128
129 to (256 – (m + 1))
(256 – m)
256
[2]
[2]
CY7C4231
Number of Words in FIFO
Number of Words in FIFO
[3]
[3]
CY7C4201
to 255
to 2047
0
1 to n
(n + 1) to 2048
(4096 – m)
4096
[2]
CY7C4241
[3]
0
1 to n
(n + 1) to 256
257 to (512 – (m + 1))
(512 – m)
512
to 4095
(512 – m),
CY7C4241 (4K – m), and CY7C4251 (8K – m). PAF is set HIGH
by the LOW-to-HIGH transition of WCLK when the number of
available memory locations is greater than m.
Table 2. Writing the Offset Registers
LD
0
0
1
1
[2]
WEN
[3]
0
1
0
1
to 511
CY7C4211
0
1 to n
(n + 1) to 4096
(8192 – m)
8192
CY7C4221
WCLK
[2]
CY7C4251
CY7C4421/4201/4211/4221
[1]
[3]
to 8191
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
No Operation
Write Into FIFO
No Operation
(1K – m),
CY7C4231/4241/4251
FF
FF
H
H
H
H
H
H
H
H
H
H
L
L
CY7C4231
Selection
PAF
PAF
H
H
H
H
H
H
H
H
L
L
L
L
Page 7 of 20
PAE
PAE
H
H
H
H
H
H
H
H
L
L
L
L
(2K – m),
EF
EF
H
H
H
H
H
H
H
H
H
H
L
L
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