IDT6116LA120TDB

Manufacturer Part NumberIDT6116LA120TDB
ManufacturerIDT, Integrated Device Technology Inc
IDT6116LA120TDB datasheet
 


Specifications of IDT6116LA120TDB

Density16KbAccess Time (max)120ns
Sync/asyncAsynchronousArchitectureNot Required
Clock Freq (max)Not RequiredMHzOperating Supply Voltage (typ)5V
Address Bus11bPackage TypeCDIP
Operating Temp Range-55C to 125CNumber Of Ports1
Supply Current85mAOperating Supply Voltage (min)4.5V
Operating Supply Voltage (max)5.5VOperating Temperature ClassificationMilitary
MountingThrough HolePin Count24
Word Size8bNumber Of Words2K
Lead Free Status / RoHS StatusNot Compliant  
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IDT6116SA/LA
CMOS Static RAM 2K (16K x 8-Bit)
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)
ADDRESS
CS
t
AS
WE
DATA
PREVIOUS DATA VALID
OUT
DATA
IN
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)
ADDRESS
CS
t
AS
WE
DATA
IN
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW CS and a LOW WE.
is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
3. t
WR
4. During this period, the I/O pins are in the output state and the input signals must not be applied.
5. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state.
6. Transition is measured ±500mV from steady state.
7. OE is continuously HIGH. If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of t
to turn off and data to be placed on the bus for the required t
. For a CS controlled write cycle, OE may be LOW with no degradation to t
is the specified t
WP
Military, Commercial, and Industrial Temperature Ranges
t
WC
t
AW
WP (7)
t
(6)
t
WHZ
(4)
t
DW
DATA VALID
t
WC
t
AW
t
CW
t
DW
DATA VALID
. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse
DW
.
CW
6.42
9
(1,2,5,7)
(3)
t
WR
(6)
t
CHZ
(6)
t
OW
(4)
DATA
VALID
t
DH
3089 drw 09
(1,2,3,5,7)
(3)
t
WR
t
DH
3089 drw 10
or (t
+ t
) to allow the I/O drivers
WP
WHZ
DW
,
,