CS1311 National Semiconductor, CS1311 Datasheet
CS1311
Specifications of CS1311
Related parts for CS1311
CS1311 Summary of contents
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... Since the SCx200 is not decoding the media locally able to go into a lower power state. When the CS1301/CS1311 is not decoding media, it uses almost no power. Additionally, since the architecture is designed for decoding media, fewer CS1301/CS1311 cycles are required ...
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... Process 0.25-micron CMOS — Packaged in a 292-terminal TEPBGA (Thermally Enhanced Plastic Ball Grid Array) Power supply: — CS1301: 2.5V Core; 3.3V I/O (5V tolerant) — CS1311: 2.2V Core; 3.3V I/O (5V tolerant) Consumption 1300 mA; 3.5W Power-down 300 mA Case Temperature 0° to 85°C Central Processing Unit Clock speed: — ...
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System Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... The CS1301/CS1311 was designed general pur- pose media data processor. As such, the CS1301/CS1311 is capable of far more than the current National CS1301/ CS1311 solution. National is providing the device as part of a complete solution and supporting these target solutions only. Refer to the document titled “CS1301/CS1311 Multi- Media Companion: System Architecture and Software Solution” ...
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... Table 2-1 shows the types of I/O circuits used by the CS1301/CS1311 devices. Note that the # symbol in a sig- nal name indicates that the active or asserted state occurs when the signal low voltage level. Otherwise, the sig- nal is asserted when at a high voltage level ...
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... MDQ28 MDQ29 MDQ31 MDQ22 MDQ20 MDQ17 MMA9 MMA7 MMA4 MMCK0 MMA3 MMA1 MMA11 MMA13 MCS# MDQ14 MDQ12 MDQ10 MCE0 MDQ0 Note: Signal names have been abbreviated in this figure due to space constraints. = GND Connection = CS1301 2.5V Core Power Connection; CS1311 2.2V Core Power Connection = 3.3V I/O Power Connection Figure 2-2. 292-TEPBGA Ball Assignment Diagram www.national.com ...
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Table 2-2. Ball Assignment Sorted by Ball Number Ball No. Signal Name Type A1 PCI_AD23 I/O A2 PCI_IDSEL I A3 PCI_AD24 I/O A4 PCI_AD27 I/O A5 PCI_AD28 I/O A6 PCI_AD31 I/O A7 PCI_INTD# I/OD A8 PCI_INTB# I/O/OD A9 SSI_IO1 I ...
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Table 2-2. Ball No. Signal Name Type L9 V GND SS L10 V GND SS L11 V GND SS L12 V GND SS L13 V GND SS L17 V PWR CC L18 V PWR CC L19 V GND SSQ L20 ...
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Table 2-3. Ball Assignment Sorted Alphabetically by Signal Name Signal Name Ball No. Signal Name AI_OSCLK B15 MM_DQ11 AI_SCK A16 MM_DQ12 AI_SD C15 MM_DQ13 AI_WS B16 MM_DQ14 AO_OSCLK B14 MM_DQ15 AO_SCK A14 MM_DQ16 AO_SD1 B13 MM_DQ17 AO_SD2 A13 MM_DQ18 AO_SD3 ...
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... I External General Purpose Clock Source for Timers. Maximum 40 MHz. I CS1301/CS1311 RESET Input. This pin can be tied to the PCI_RST# signal in PCI bus systems. Upon releasing RESET, the CS1301/CS1311 initiates its boot protocol. PWR PCI Voltage Reference. Determines the mode of operation of the PCI pins ...
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Memory Interface Signals (Continued) Ball Signal Name No. MM_A[13:00] See Table 2-3 "Ball Assign- ment Sorted Alphabeti- cally by Signal Name" on page 9 MM_DQ[31:00] See Table 2-3 "Ball Assign- ment Sorted Alphabeti- cally by Signal Name" on page ...
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... ID Select. Used as chip select during configuration read/write cycles. I/O Device Select Sustained TRI-STATE. Indicates whether any device on the bus has been selected. O Request. Driven by the CS1301/CS1311 as a PCI bus master to request use of the PCI bus. I Grant. Indicates to the CS1301/CS1311 that access to the PCI bus has been granted. ...
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... If configured as an input (power-up default): A positive transition on this incoming video clock pin samples VI_DATA[09:00] if VI_DVALID is high. If VI_DVALID is low, VI_DATA[09:00] is ignored. Clock and data rates MHz are supported. The CS1301/CS1311 supports an addi- tional mode where VI_DATA[09:08] in message passing mode are not affected by the VI_DVALID signal. ...
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... AI_SCK is an input. AI_SCK receives the serial bit clock from the external A/D subsystem. This clock is treated as fully asynchronous to the CS1301/CS1311 main clock. When the AI module is programmed as the serial-interface timing mas- ter, AI_SCK is an output. AI_SCK drives the serial clock for the external A/D subsystem ...
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... S/PDIF Data Out. Self-clocking serial data stream as per IEC958, with 1937 extensions. Note that the low impedance output buffer requires 33W series terminator close to CS1301/CS1311 in order to match the board trace impedance. This series terminator must be part of the voltage divider needed to create the coaxial output through the AC isola- tion transformer ...
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JTAG Interface Signals Ball Signal Name No. JTAG_TDI F20 JTAG_TDO F18 JTAG_TCK F19 JTAG_TMS E20 2.2.11 Test and Measurement Interface Signals Ball Signal Name No. BOOT_CLK T20 TESTMODE P19 SCANCPU D20 2.2.12 Synchronous Serial Interface (SSI) Ball Signal Name ...
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... DC floating connected on-chip other connection to board ground is needed; such a connection would create a ground loop. PWR 2.5V CS1301 Core Power Connection (Total of 24). 2.2V CS1311 Core Power Connection (Total of 24). PWR 3.3V I/O Power Connection (Total of 24). GND Ground Connection (Total of 50). ...
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REFERENCE VOLTAGES Outputs always drive to a level determined by the 3.3V I/O voltage, with the exception of Open Drain mode outputs. VREF_PCI Determined Mode PCI_AD00 PCI_AD27 TRI_USERIRQ PCI_AD01 PCI_AD28 TRI_TIMER_CLK PCI_AD02 PCI_AD29 JTAG_TDI PCI_AD03 PCI_AD30 JTAG_TDO PCI_AD04 PCI_AD31 ...
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Package Specifications Figure 3-1 provides the mechanical package outline for the 292-Terminal TEPBGA (Thermally Enhanced Ball Grid Array) package. NOTES: UNLESS OTHERWISE SPECIFIED. 1) SOLDER BALL COMPOSITION: SN 63%, PB 37%. 2) DIMENSION IS MEASURED AT THE MAXIMUM SOLDER ...
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... CS1301 CS1301 CS1311 CS1311 Note: Due to licensing agreements, the CS1301/CS1311 can only be purchased by those customers using a Geode processor-based design. A.2 PRODUCT BRIEF REVISION HISTORY This section is a report of the revision/creation process of the product brief for the Geode Device Number. Any revi- sions (i ...
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... NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the ...