DSP56321VF275 Freescale, DSP56321VF275 Datasheet - Page 10

• Manufacturer Part Number: DSP56321VF275
• Manufacturer: Freescale

Specifications of DSP56321VF275

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 275MHz
• Mips: 275
• Device Input Clock Speed: 275MHz
• Ram Size: 576KB
• Operating Supply Voltage (typ): 1.6/3.3V
• Operating Supply Voltage (min): 1.5/3/3/3/3/3/3V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

Signals/Connections
1.4 External Memory Expansion Port (Port A)
Note: When the DSP56321 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-
1.4.1
1.4.2
1.4.3
1-4
D[0–23]
AA[0–3]
RD
WR
A[0–17]
Signal Name
Signal Name
Signal Name
states the relevant Port A signals:
External Address Bus
External Data Bus
External Bus Control
Input/ Output
Output
Output
Output
Output
Type
Type
Type
Ignored Input
Tri-stated
Tri-stated
Tri-stated
Reset, Stop, or
Tri-stated
State During
State During
State During
Reset, Stop,
Table 1-5.
Table 1-7.
Table 1-6.
or Wait
Reset
Wait
DSP56321 Technical Data, Rev. 11
A[0–17]
External Address Bus Signals
,
External Bus Control Signals
Last state:
Input : Ignored
Output :
Last value
Address Attribute—When defined as AA, these signals can be used as chip
selects or additional address lines. The default use defines a priority scheme
under which only one AA signal can be asserted at a time. Setting the AA priority
disable (APD) bit (Bit 14) of the Operating Mode Register, the priority
mechanism is disabled and the lines can be used together as four external lines
that can be decoded externally into 16 chip select signals.
Read Enable—When the DSP is the bus master, RD is an active-low output that
is asserted to read external memory on the data bus (D[0–23]). Otherwise, RD is
tri-stated.
Write Enable—When the DSP is the bus master, WR is an active-low output
that is asserted to write external memory on the data bus (D[0–23]). Otherwise,
the signals are tri-stated.
D[0–23]
Address Bus—When the DSP is the bus master, A[0–17] are active-high
outputs that specify the address for external program and data memory
accesses. Otherwise, the signals are tri-stated. To minimize power dissipation,
A[0–17] do not change state when external memory spaces are not being
accessed.
External Data Bus Signals
State During
Stop or Wait
,
AA[0
–
3]
,
Data Bus—When the DSP is the bus master, D[0–23] are
active-high, bidirectional input/outputs that provide the
bidirectional data bus for external program and data
memory accesses. Otherwise, D[0–23] drivers are tri-
stated. If the last state is output, these lines have weak
keepers to maintain the last output state if all drivers are tri-
stated.
RD
,
WR
Signal Description
Signal Description
,
BB
.
Signal Description
Freescale Semiconductor