DSP56301AG100 Freescale, DSP56301AG100 Datasheet - Page 10

• Manufacturer Part Number: DSP56301AG100
• Manufacturer: Freescale

Specifications of DSP56301AG100

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: TQFP
• Lead Free Status / RoHS Status: Compliant

Signals/Connections
1.5 External Memory Expansion Port (Port A)
Note: When the DSP56301 enters a low-power stand-by mode (Stop or Wait), it releases bus mastership and tri-
1.5.1
1.5.2
1-6
PINIT/NMI
A[0–23]
D[0–23]
Signal Name
Signal Name
Signal Name
states the relevant Port A signals:
BCLK
occur and then returns to the Wait mode.
External Address Bus
External Data Bus
. If hardware refresh of external DRAM is enabled, Port A exits the Wait mode to allow the refresh to
Input
Output
Input/Output
Type
Type
Type
Table 1-5.
Input
Tri-stated
Tri-stated
State During
State During
State During
Table 1-6.
Table 1-7.
Reset
Reset
Reset
DSP56301 Technical Data, Rev. 10
A[0–23]
Phase Lock Loop Signals (Continued)
External Address Bus Signals
,
PLL Initial/Non-Maskable Interrupt
During assertion of RESET, the value of PINIT/NMI is written into the PLL
Enable (PEN) bit of the PLL control register, determining whether the PLL is
enabled or disabled. After RESET deassertion and during normal instruction
processing, the PINIT/NMI Schmitt-trigger input is a negative-edge-triggered
Non-Maskable Interrupt (NMI) request internally synchronized to CLKOUT.
PINIT/NMI can tolerate 5 V.
D[0–23]
Address Bus
When the DSP is the bus master, A[0–23] specify the address for external
program and data memory accesses. Otherwise, the signals are tri-stated. To
minimize power dissipation, A[0–23] do not change state when external
memory spaces are not being accessed.
Data Bus
When the DSP is the bus master, D[0–23] provide the bidirectional data bus
for external program and data memory accesses. Otherwise, D[0–23] are tri-
stated.
External Data Bus Signals
,
AA0/RAS0
–
AA3/RAS3
Signal Description
Signal Description
Signal Description
,
RD
,
WR
,
BB
Freescale Semiconductor
,
CAS
,
BCLK
, and