DSP56301AG100 Freescale, DSP56301AG100 Datasheet - Page 3

• Manufacturer Part Number: DSP56301AG100
• Manufacturer: Freescale

Specifications of DSP56301AG100

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 100MHz
• Mips: 100
• Device Input Clock Speed: 100MHz
• Ram Size: 24KB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: TQFP
• Lead Free Status / RoHS Status: Compliant

DSP56301 Features
Freescale Semiconductor
High-Performance DSP56300 Core
Internal Peripherals
Internal Memories
Program RAM
4096 × 24 bits
3072 × 24 bits
2048 × 24 bits
1024 × 24 bits
Size
• 80/100 million instructions per second (MIPS) with a 80/100 MHz clock at 3.0–3.6 V
• Object code compatible with the DSP56000 core with highly parallel instruction set
• Data Arithmetic Logic Unit (Data ALU) with fully pipelined 24 × 24-bit parallel Multiplier-
• Program Control Unit (PCU) with Position Independent Code (PIC) support, addressing modes
• Direct Memory Access (DMA) with six DMA channels supporting internal and external
• Phase Lock Loop (PLL) allows change of low-power Divide Factor (DF) without loss of lock
• Hardware debugging support including On-Chip Emulation (OnCE™) module, Joint Test Action
• 32-bit parallel PCI/Universal Host Interface (HI32), PCI Rev. 2.1 compliant with glueless
• Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three
• Serial communications interface (SCI) with baud rate generator
• Triple timer module
• Up to forty-two programmable general-purpose input/output (GPIO) pins, depending on which
• 3 K × 24-bit bootstrap ROM
• 8 K × 24-bit internal RAM total
• Program RAM, Instruction Cache, X data RAM, and Y data RAM sizes are programmable:
Accumulator (MAC), 56-bit parallel barrel shifter (fast shift and normalization; bit stream
generation and parsing), conditional ALU instructions, and 24-bit or 16-bit arithmetic support
under software control
optimized for DSP applications (including immediate offsets), internal instruction cache
controller, internal memory-expandable hardware stack, nested hardware DO loops, and fast
auto-return interrupts
accesses; one-, two-, and three-dimensional transfers (including circular buffering); end-of-
block-transfer interrupts; and triggering from interrupt lines and all peripherals
and output clock with skew elimination
Group (JTAG) Test Access Port (TAP)
interface to other DSP563xx buses or ISA interface requiring only 74LS45-style buffers
transmitters (allows six-channel home theater)
peripherals are enabled
Instruction Cache
1024 × 24-bit
1024 × 24-bit
Size
DSP56301 Technical Data, Rev. 10
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0
X Data RAM Size Y Data RAM Size
2048 × 24 bits
2048 × 24 bits
3072 × 24 bits
3072 × 24 bits
2048 × 24 bits
2048 × 24 bits
3072 × 24 bits
3072 × 24 bits
Instruction
disabled
disabled
enabled
enabled
Cache
disabled
disabled
Switch
enabled
enabled
Mode
iii