PPC440EPX-SUA667T Applied Micro Circuits Corporation, PPC440EPX-SUA667T Datasheet - Page 14

• Manufacturer Part Number: PPC440EPX-SUA667T
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC440EPX-SUA667T

• Family Name: 440EPx
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 667MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5/3.3V
• Operating Supply Voltage (max): 1.6/3.45V
• Operating Supply Voltage (min): 1.425/3.15V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 680
• Package Type: TEBGA
• Lead Free Status / RoHS Status: Compliant

440EPx – PPC440EPx Embedded Processor
Ethernet Controller
Ethernet support provided by the PPC440EPx interfaces to the physical layer but the PHY is not included on the
chip:
DMA-to-PLB3 (64-bit) Controller
This DMA controller provides a DMA interface between OPB0 and PLB3.
Features include:
DMA-to-PLB4 (128-bit) Controller
This DMA controller provides a DMA interface between the OPB1 dedicated to the USB 2.0 device ports and
PLB4.
Features include:
14
• External master interface
• Two 10/100/1000 interfaces running in full- and half-duplex modes providing:
• Supports the following transfers:
• Four channels
• Scatter/Gather capability for programming multiple DMA operations
• 32-byte buffer
• 8-, 16-, 32-bit peripheral support (OPB and external)
• 32-bit addressing
• Address increment or decrement
• Supports internal and external peripherals
• Support for memory mapped peripherals
• Support for peripherals running on slower frequency buses
• Four independent channels supporting internal USB 2.0 Device endpoints 1 and 2
• Support for memory-to-memory, peripheral-to-memory, and memory-to-peripheral transfers
• Scatter/gather capability
• 128-byte buffer with programmable thresholds
– Write posting from external master
– Read prefetching on PLB for external master reads
– Bursting capable from external master
– Allows external master access to all non-EBC PLB slaves
– External master can control EBC slaves for access
– One Gigabit Media Independent Interface (GMII)
– One Media Independent Interface (MII)
– Two Reduced Gigabit MII (RGMII)
– Two Serial MII (SMII) at 100/10Mbps.
– Packet reject support
– Jumbo frame support
– DMA capability
– Interrupt coalescence
– Memory-to-memory transfers
– Buffered peripheral to memory transfers
– Buffered memory to peripheral transfers
Revision 1.30 – February 27, 2009
Data Sheet
AMCC Proprietary