MCIMX351AJQ5C Freescale, MCIMX351AJQ5C Datasheet - Page 16
MCIMX351AJQ5C
Manufacturer Part Number
MCIMX351AJQ5C
Description
Manufacturer
Freescale
Datasheet
1.MCIMX351AJQ5C.pdf
(148 pages)
Specifications of MCIMX351AJQ5C
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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4.3
This section provides power-up and power-down sequence guidelines for the i.MX35 processor.
16
Stop
Static
Note: Typical column: T
Note: Maximum column: T
Power
Mode
VDD1,2,3,4 = 1.1 V (min.)
ARM is in wait for interrupt mode.
MAX is halted
L2 cache is kept powered.
L2 cache control logic off.
AWB enabled.
MCU PLL is off.
PER PLL is off.
All clocks are gated off.
OSC 24 MHz is on
OSC audio is off
RNGC internal osc is off
VDD1,2,3,4 = 1.1 V (min.)
ARM is in wait for interrupt mode.
MAX is halted
L2 cache is kept powered.
L2 cache control logic off.
AWB enabled.
MCU PLL is off.
PER PLL is off.
All clocks are gated off.
OSC 24MHz is on
OSC audio is off
RNGC internal osc is off
Supply Power-Up/Power-Down Requirements and Restrictions
Any i.MX35 board design must comply with the power-up and power-down
sequence guidelines as described in this section to guarantee reliable
operation of the device. Any deviation from these sequences can result in
irreversible damage to the i.MX35 processor (worst-case scenario).
A
Description
= 25 °C
A
i.MX35 Applications Processors for Automotive Products, Rev. 9
= 85 °C
Table 10. i.MX35 Power Modes (continued)
1.1
820
CAUTION
Typ.
QVCC (ARM/L2
mA
Peripheral)
µA
77
72
Max.
mA
mA
400
50
Typ.
MVDD/PVDD
µA
µA
2.2
1.7
Max.
mA
mA
Freescale Semiconductor
1.2
OSC_AUDO_VDD
24
Typ.
OSC24M_VDD
mA
µA
2.2
35
Max.
mA
µA
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