MCIMX31LDVMN5D Freescale, MCIMX31LDVMN5D Datasheet - Page 52

• Manufacturer Part Number: MCIMX31LDVMN5D
• Manufacturer: Freescale

Specifications of MCIMX31LDVMN5D

• Operating Temperature (min): -20C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Electrical Characteristics
4.3.10
ETM is an ARM protocol. The timing specifications in this section are given as a guide for a TPA that
supports TRACECLK frequencies up to 133 MHz.
Figure 39
52
SD21 DQS – DQ Skew (defines the Data valid window in read cycles related to DQS).
SD22 DQS DQ HOLD time from DQS
SD23 DQS output access time from SDCLK posedge
ID
DQS (input)
DQ (input)
SDCLK
SDCLK
Figure 38. Mobile DDR SDRAM DQ versus DQS and SDCLK Read Cycle Timing Diagram
depicts the TRACECLK timings of ETM, and
ETM Electrical Specifications
SDRAM CLK and DQS related parameters are being measured from the
50% point—that is, high is defined as 50% of signal value and low is
defined as 50% of signal value.
The timing parameters are similar to the ones used in SDRAM data
sheets—that is,
are driven by the ESDCTL at the negative edge of SDCLK and the
parameters are measured at maximum memory frequency.
Table 38. Mobile DDR SDRAM Read Cycle Timing Parameters
SD23
Table 38
Figure 39. ETM TRACECLK Timing Diagram
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
SD21
Data
Parameter
indicates SDRAM requirements. All output signals
SD22
Data
NOTE
Data
Table 39
Data
lists the timing parameters.
Data
Data
tDQSCK
Symbol
tDQSQ
tQH
Freescale Semiconductor
Data
Min Max Unit
2.3
—
—
Data
0.85
6.7
—
ns
ns
ns