MCIMX31DVMN5D Freescale, MCIMX31DVMN5D Datasheet

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... The performance of the MCIMX31 is boosted by a multi-level cache system, and features peripheral devices This document contains information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2005–2008. All rights reserved. Document Number: MCIMX31_5 Rev. 4.3, 12/2009 ...

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... Multiple clock and power domains — Independent gating of power domains • Multiple communication and expansion ports including a fast parallel interface to an external graphic accelerator (supporting major graphic accelerator vendors) • Security 2 MCIMX31/MCIMX31L Technical Data, Rev. 4.3 ® tightly-coupled Vector Freescale Semiconductor ...

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... Part Number Silicon Revision MCIMX31DVKN5D! 2.0.1 MCIMX31LDVKN5D! 2.0.1 MCIMX31CVKN5D! 2.0.1 MCIMX31LCVKN5D! 2.0.1 MCIMX31DVMN5D! 2.0.1 MCIMX31LDVMN5D! 2.0.1 MCIMX31CJKN5D 2.0.1 MCIMX31LCJKN5D 2.0.1 1 Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not available from Freescale for import or sale in the United States prior to September 2010: ...

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... MCIMX31/MCIMX31L Technical Data, Rev. 4.3 Tamper Detection Mouse Keyboard AP Peripherals AUDMUX Power SSI (2) Management UART ( (3) FIR CSPI (3) PWM USB Host (2) USB-OTG KPP Keypad GPIO CCM Serial ® 1-WIRE EPROM IIM GPU* GPS ATA Hard Drive PC USB Card Host/Device Freescale Semiconductor ...

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... The ARM Application Processor (AP) and other subsystems address the needs of the personal, wireless, and portable product market with integrated peripherals, advanced processor core, and power management capabilities. Freescale Semiconductor Functional Description and Application Information Table 2. MCIMX31 Core Brief Description MCIMX31/MCIMX31L Technical Data, Rev. 4.3 ™ ...

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... Mbit/s, 1.152 Mbit/s medium infrared (MIR) physical layer protocol and 4Mbit/s fast infrared (FIR) physical layer protocol defined by IrDA, Rev. 1.4. MCIMX31/MCIMX31L Technical Data, Rev. 4.3 Section/ Page 4.3.4/24 4.3.5/25 4.3.6/34 4.3.3/23 — 4.3.7/34 4.3.8/35 — — 4.3.9.3/44, 4.3.9.1/36, 4.3.9.2/39 — 4.3.10/52 4.3.11/53 Freescale Semiconductor ...

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... Checkers Freescale Semiconductor Functional Description and Application Information Brief Description The Fusebox is a ROM that is factory configured by Freescale. The GPIO provides several groups of 32-bit bidirectional, general purpose I/O. This peripheral provides dedicated general-purpose signals that can be configured as either inputs or outputs. The GPT is a multipurpose module used to measure intervals or generate periodic output ...

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... Host 1 Port and the OTG transceiver. The WDOG module protects against system failures by providing a method for the system to recover from unexpected events or programming errors. MCIMX31/MCIMX31L Technical Data, Rev. 4.3 Section/ Page — 4.3.19/87 — 4.3.20/88 4.3.21/92 4.3.22/94 — 4.3.23/102 — Freescale Semiconductor ...

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... CE_CONTROL is a reserved input and must be externally tied to GND through a 1 kΩ resistor. • TTM_PAD This is for Freescale factory use only. Control bits indicate that the pull-up/down is disabled. However, the TTM_PAD is actually connected to an on-chip pull-down device. Users must either float this signal or tie it to GND. ...

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... Topic appears … on page 10 on page 11 on page 13 on page 14 on page 14 on page 16 on page 18 Table 8, Min Max –0.5 1.65 max –0.5 3.3 max –0.5 NVCC +0.3 Imax –40 125 storage — 1500 V esd — 200 — 500 1 — 15 Freescale Semiconductor Units ...

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... Junction to Ambient (natural convection) Junction to Ambient (natural convection) Junction to Ambient (@200 ft/min) Junction to Ambient (@200 ft/min) Junction to Board Junction to Case (Top) Junction to Package Top (natural convection) Freescale Semiconductor × Board Single layer board (1s) Four layer board (2s2p) Single layer board (1s) Four layer board (2s2p) — ...

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... Thermal characterization parameter indicating the temperature difference between the package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. 12 NOTES MCIMX31/MCIMX31L Technical Data, Rev. 4.3 Freescale Semiconductor ...

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... Overshoot/undershoot must be controlled through printed circuit board layout, transmission line impedance matching, signal line termination, or other methods. Non-compliance to this specification may affect device reliability or cause permanent damage to the device. Freescale Semiconductor NOTE CAUTION Table 8 ...

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... DPTC functionality, specifically the voltage/frequency relation table, is dependent on CKIH frequency. At the time of publication, standard tables used by Freescale OSs provided for a CKIH frequency of 26 MHz only. Any deviation from this frequency requires an update to the OS. For more details, refer to the particular OS user's guide documentation. ...

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... V 1 The current I is during program time (t program 2 The current I is present for approximately the read access to the 8-bit word, and only applies to Silicon Rev. 1.2 read and previous. Freescale Semiconductor Symbol 1 I program I read ). program MCIMX31/MCIMX31L Technical Data, Rev. 4.3 ...

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... MCIMX31/MCIMX31L Technical Data, Rev. 4.3 for Silicon Revision 2.0.1 FVCC + MVCC QVCC1 QVCC4 + SVCC + UVCC (ARM) (L2) (PLL) Max Typ Max Typ Max — — — 0.02 0.10 2.20 — — 0.02 0.10 25.00 0.03 0.29 3.60 4.40 Freescale Semiconductor Unit ...

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... All clocks are gated off • All modules are off (by programming CGR[2:0] registers) • RNGA oscillator is off • No external resistive loads 1 Typical column 25°C 2 Maximum column 70°C Freescale Semiconductor 1, 2 ° ° QVCC (Peripheral) Typ Max Typ 0 ...

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... NVCC1, and NVCC3 through NVCC10 do not need to be powered up in the order shown. NVCC6 and NVCC9 must be at the same voltage potential. These supplies are connected together on-chip to optimize ESD damage immunity. 18 NOTE CAUTION MCIMX31/MCIMX31L Technical Data, Rev. 4.3 Freescale Semiconductor ...

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... IOQVDD, NVCC1, NVCC3–10, NVCC2, NVCC21, NVCC22 FVCC, MVCC, SVCC, UVCC 4 Release POR Figure 3. Option 2 Power-Up Sequence (Silicon Revision 2.0.1) Freescale Semiconductor Notes: 1 The board design must guarantee that supplies reach 90% level before transition to the next state, using Power Management IC or other means. ...

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... MCIMX31/MCIMX31L Technical Data, Rev. 4.3 Table 8 for temperature and supply Min Typ Max NVCC –0.15 — — 0.8*NVCC — — — — 0.15 — — 0.2*NVCC — — –2 –4 –8 — — –4 –6 –8 — — Freescale Semiconductor Units ...

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... Ranges," on page 13 for temperature and supply voltage ranges. NVCC for Table 15. DDR (Double Data Rate) I/O DC Electrical Parameters Parameter High-level output voltage Low-level output voltage High-level output current Low-level output current Freescale Semiconductor Symbol Test Conditions I V =0.2*NVCC OL_F OL Std Drive ...

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... NVCC NVCC+0.3 –0.3 0 0.3*NVCC ±2 — — Table 17 for fast general I/O, and NVCC 80% 20% 0V PA1 1 General I/O Test Min Typ Max Condition 25 pF 0.92 1.95 3. 1.5 2.98 4. 1.52 — 4. 2.75 8. 2.79 — 8. 5.39 16.43 Freescale Semiconductor Units V V μA Units ...

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... VIL (for square wave input) VIH (for square wave input) Sinusoidal Input Amplitude Duty Cycle 1 VDD is the supply voltage of CAMP. See reference manual. 2 This value of the sinusoidal input will be measured through characterization. Freescale Semiconductor Symbol tpr tpr tpr Symbol 1 tpr tpr ...

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... MCIMX31/MCIMX31L Technical Data, Rev. 4.3 DS2502 Tx “Presence Pulse” OW2 OW3 OW4 Min Typ Max Units 480 511 — 15 — — 240 480 512 — Min Typ Max Units 60 100 120 OW5 117 120 Table 22 Freescale Semiconductor µs µs µs µs µs µs lists ...

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... This direction control signal is ata_buffer_en. When its high, the bus should drive from host to device. When its low, the bus should drive from device to host. Steering of the signal is such that contention on the host and device tri-state busses is always avoided. Freescale Semiconductor OW8 OW7 Figure 8 ...

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... MCIMX31/MCIMX31L Technical Data, Rev. 4.3 Table 23 shows ATA Value/ Contributing Factor peripheral clock frequency UDMA0 15 ns UDMA1 10 ns UDMA2, UDMA3 7 ns UDMA4 5 ns UDMA5 4 ns 5.0 ns UDMA5 4.6 ns 12.0 ns 8.5 ns 8 transceiver transceiver transceiver cable cable cable cable cable Freescale Semiconductor 1 ...

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... T > tsu + thi + tskew3 + tskew4 t0 — t0 (min) = (time_1 + time_2 + time_9 Figure 11 shows timing for PIO write, and Freescale Semiconductor Table 24 lists the timing parameters for PIO read. Figure 10. PIO Read Timing Diagram Table 24. PIO Read Timing Parameters Value Table 25 lists the timing parameters for PIO write ...

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... Figure 11. Multiword DMA (MDMA) Timing Table 25. PIO Write Timing Parameters Value Figure 13 shows timing for MDMA write, and MCIMX31/MCIMX31L Technical Data, Rev. 4.3 Controlling Variable time_1 time_2w time_9 If not met, increase time_2w time_4 time_ax time_1, time_2r, time_9 — — Table 26 lists the Freescale Semiconductor ...

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... T – (tskew1 + tskew2 + tskew6) — ton ton = time_on * T – tskew1 toff toff = time_off * T – tskew1 Freescale Semiconductor Figure 12. MDMA Read Timing Diagram Figure 13. MDMA Write Timing Diagram Value MCIMX31/MCIMX31L Technical Data, Rev. 4.3 Electrical Characteristics Controlling ...

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... UDMA in burst. Figure 14. UDMA In Transfer Starts Timing Diagram Figure 15. UDMA In Host Terminates Transfer Timing Diagram 30 Figure 15 shows timing when the UDMA in device terminates transfer, and MCIMX31/MCIMX31L Technical Data, Rev. 4.3 shows timing when the UDMA in Freescale Semiconductor ...

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... There is a special timing requirement in the ATA host that requires the internal DIOW to go only high 3 clocks after the last active edge on the DSTROBE signal. The equation given on this line tries to capture this constraint. 2. Make ton and toff big enough to avoid bus contention Freescale Semiconductor Table 27. UDMA In Burst Timing Parameters Description MCIMX31/MCIMX31L Technical Data, Rev ...

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... UDMA out burst. Figure 17. UDMA Out Transfer Starts Timing Diagram Figure 18. UDMA Out Host Terminates Transfer Timing Diagram 32 Figure 18 shows timing when the UDMA out device terminates transfer, and MCIMX31/MCIMX31L Technical Data, Rev. 4.3 shows timing when the UDMA out Freescale Semiconductor ...

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... T – tskew1 toff toff = time_off * T – tskew1 Freescale Semiconductor Value MCIMX31/MCIMX31L Technical Data, Rev. 4.3 Electrical Characteristics Controlling Variable time_ack time_env time_dvs time_dvh time_cyc time_cyc — ...

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... Figure 20. CSPI Master Mode Timing Diagram SSx CS1 SCLK CS7 CS8 MISO CS9 CS10 MOSI Figure 21. CSPI Slave Mode Timing Diagram 34 CS2 CS3 CS3 CS2 CS2 CS3 CS3 CS2 MCIMX31/MCIMX31L Technical Data, Rev. 4.3 Table 29 lists the CS6 CS5 CS4 CS6 CS5 CS4 Freescale Semiconductor ...

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... Pre-multiplier (FPM) enable mode) Predivision factor (PD bits) PLL reference frequency range after Predivider PLL output frequency range: MPLL and SPLL Maximum allowed reference clock phase noise. Frequency lock time (FOL mode or non-integer MF) Freescale Semiconductor Table 29. CSPI Interface Timing Parameters Symbol RISE/FALL ...

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... Command MCIMX31/MCIMX31L Technical Data, Rev. 4.3 Max Unit Comments 100 µs In addition to the frequency < 50 kHz modulation kHz < F < 300 kHz modulation > 300 kHz modulation 5.2 ns Measured on CLKO pin 420 ps Measured on CLKO pin Figure 22, Figure 23, Figure NF2 NF4 Freescale Semiconductor 24, ...

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... NFCLE NFCE NFWE NFALE NFIO[7:0] Figure 23. Address Latch Cycle Timing DIagram NFCLE NFCE NFWE NFALE NFIO[15:0] Figure 24. Write Data Latch Cycle Timing DIagram Freescale Semiconductor NF1 NF4 NF3 NF10 NF11 NF5 NF7 NF6 NF8 NF9 Address NF1 NF3 NF10 NF11 NF5 ...

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... Table 30, "DPLL Specifications," on page MCIMX31/MCIMX31L Technical Data, Rev. 4.3 1 Example Timing for ≈ NFC Clock 33 MHz 2 Unit Min Max 29 — — — — — — — — 27.5 ns 180 — — — ns 12.5 — — — ns 35. Freescale Semiconductor ...

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... Input data, ECB and DTACK all captured according to BCLK rising edge time. WEIM module, and Table 32 lists the timing parameters. Freescale Semiconductor NOTE MCIMX31/MCIMX31L Technical Data, Rev. 4.3 Electrical Characteristics Figure 26 ...

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... ECB WE17 WE20 DTACK WE19 Figure 26. WEIM Bus Timing Diagram Table 32. WEIM Bus Timing Parameters Parameter MCIMX31/MCIMX31L Technical Data, Rev. 4.3 WE2 WE4 WE6 WE8 WE10 WE12 WE14 Min Max Unit –0.5 2.5 ns –0 – – – – – Freescale Semiconductor ...

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... Test conditions: load capacitance, 25 pF. Recommended drive strength for all controls, address, and BCLK is Max drive. Figure 27, Figure 28, Figure 29, basic WEIM accesses to external memory devices with the timing parameters mentioned in Table 32 for specific control parameter settings. Freescale Semiconductor Parameter FCE=1 FCE NOTE Figure 30, Figure ...

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... Figure 28. Asynchronous Memory Timing Diagram for Write Access— 42 WE1 V1 WE3 WE11 WE7 WE9 V1 WE15 WE1 V1 WE3 WE5 WE11 WE12 WE9 WE10 V1 WE13 WSC=1, EBWA=1, EBWN=1, LBN=1 MCIMX31/MCIMX31L Technical Data, Rev. 4.3 WE2 Next Address WE4 WE12 WE8 WE10 WE16 WE2 Next Address WE4 WE6 WE14 Freescale Semiconductor ...

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... ADDR Last Valid Addr WE3 CS[x] WE5 RW WE11 LBA OE WE9 EB[y] ECB DATA WE13 Figure 30. Synchronous Memory TIming Diagram for Burst Write Access— Freescale Semiconductor Address V1 WE12 WE18 WE18 WE17 WE17 WE16 WE16 V1 V1+2 Halfword Halfword WE15 WE15 WSC=2, SYNC=1, DOL=0 ...

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... WE7 WSC=7, LBA=1, LBN=1, LAH=1, OEA=7 Figure 36, Figure 37, and Figure 38 MCIMX31/MCIMX31L Technical Data, Rev. 4.3 WE14 Write Data WE13 WE4 WE6 WE10 WE16 Read Data WE15 WE4 WE8 WE10 depict the timings pertaining to the Table 33, Table 34, Table 35, Freescale Semiconductor Table 36, ...

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... SDRAM clock cycle time SD4 CS, RAS, CAS, WE, DQM, CKE setup time SD5 CS, RAS, CAS, WE, DQM, CKE hold time SD6 Address setup time SD7 Address hold time SD8 SDRAM access time Freescale Semiconductor SD1 SD4 SD5 SD4 SD5 SD5 SD7 COL/BA SD8 SD10 ...

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... ESDCTL at the negative edge of SDCLK and the parameters are measured at maximum memory frequency. 46 Parameter NOTE indicates SDRAM requirements. All output signals MCIMX31/MCIMX31L Technical Data, Rev. 4.3 Symbol Min Max tOH 1.8 — tRC 10 — clock Freescale Semiconductor Unit ns ...

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... CS, RAS, CAS, WE, DQM, CKE setup time SD5 CS, RAS, CAS, WE, DQM, CKE hold time SD6 Address setup time SD7 Address hold time SD11 Precharge cycle period SD12 Active to read/write command delay Freescale Semiconductor SD1 SD3 SD11 SD5 SD12 SD7 ROW / BA Parameter 1 1 MCIMX31/MCIMX31L Technical Data, Rev. 4.3 ...

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... SD1 SD11 SD10 Figure 35. SDRAM Refresh Timing Diagram Symbol tCH tCL MCIMX31/MCIMX31L Technical Data, Rev. 4.3 Symbol Min Max tDS 2.0 — tDH 1.3 — SD2 SD3 SD10 ROW/BA Min Max 3.4 4.1 3.4 4.1 Freescale Semiconductor Unit ns ns Unit ns ns ...

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... The timing parameters are similar to the ones used in SDRAM data sheets—that is, Table 35 are driven by the ESDCTL at the negative edge of SDCLK and the parameters are measured at maximum memory frequency. Freescale Semiconductor Symbol tCK tAS tAH 1 tRP ...

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... The clock will continue to run unless both CKEs are low. Then the clock will be stopped in low state. Table 36. SDRAM Self-Refresh Cycle Timing Parameters ID Parameter SD16 CKE output delay time 50 SD16 NOTE Symbol tCKS MCIMX31/MCIMX31L Technical Data, Rev. 4.3 SD16 Min Max Unit 1.8 — ns Freescale Semiconductor ...

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... The timing parameters are similar to the ones used in SDRAM data sheets—that is, Table 37 are driven by the ESDCTL at the negative edge of SDCLK and the parameters are measured at maximum memory frequency. Freescale Semiconductor SD18 SD17 Data Data Data Data ...

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... NOTE indicates SDRAM requirements. All output signals Table 39 Figure 39. ETM TRACECLK Timing Diagram MCIMX31/MCIMX31L Technical Data, Rev. 4.3 Data Data Data Data Symbol Min Max Unit tDQSQ — 0.85 tQH 2.3 — tDQSCK — 6.7 lists the timing parameters. Freescale Semiconductor ...

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... Program time for eFuse 1 The program length is defined by the value defined in the epm_pgm_length[2:0] bits of the IIM module. The value to program is based kHz clock source (4 * 1/32 kHz = 125 µs). Freescale Semiconductor Frequency dependent Figure 40. Trace Data Timing Diagram Parameter Table 41. Fusebox Timing Characteristics ...

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... C-bus specification) Freescale Semiconductor START Unit μs μs μs 2 μs μs μs μs ns μ ...

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... Motorola MC30300 (Python) National Semiconductor LM9618 1 Freescale Semiconductor does not recommend one supplier over another and in no way suggests that these are the only camera suppliers. 2 These sensors not validated at time of publication. 4.3.14.2 Functional Description There are three timing modes supported by the IPU. ...

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... Figure 43. Non-Gated Clock Mode Timing Diagram 56 Active Line n+1th frame invalid 1st byte Section 4.3.14.2.2, “Gated Clock Figure n+1th frame invalid 1st byte MCIMX31/MCIMX31L Technical Data, Rev. 4.3 1st byte Mode”), 43. All incoming pixel clocks are 1st byte Freescale Semiconductor ...

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... IPU Display Interfaces — 4.3.15.1 Supported Display Components Table 45 lists the known supported display components at the time of publication. Freescale Semiconductor is that of a Motorola sensor. Some other sensors may have a slightly Table 44 lists the timing parameters. 1/IP1 IP2 IP3 Figure 44. Sensor Interface Timing Diagram ...

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... Digital video encoders Analog Devices (for TV) Crystal (Cirrus Logic) Focus 1 Freescale Semiconductor does not recommend one supplier over another and in no way suggests that these are the only display component suppliers. 2 These display components not validated at time of publication. 4.3.15.2 Synchronous Interfaces 4.3.15.2.1 ...

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... Start of line IP5 DISPB_D3_CLK DISPB_D3_HSYNC DISPB_D3_DRDY DISPB_D3_DATA Figure 46. TFT Panels Timing Diagram—Horizontal Sync Pulse Figure 47 depicts the vertical timing (timing of one frame). All figure parameters shown are programmable. Freescale Semiconductor LINE 2 LINE 3 LINE IP7 IP9 IP8 MCIMX31/MCIMX31L Technical Data, Rev. 4.3 ...

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... BGYP – FH) * Tsw , HSP_CLK_PERIOD DISP3_IF_CLK_PER_WR ± ----------------------------------------------------------------- - + 0.5 0.5 HSP_CLK_PERIOD DISP3_IF_CLK_PER_WR ⋅ ----------------------------------------------------------------- - Tdicp = T HSP_CLK HSP_CLK_PERIOD MCIMX31/MCIMX31L Technical Data, Rev. 4.3 End of frame Start of frame IP15 IP12 and Figure 47. Value 1 DISP3_IF_CLK_PER_WR ----------------------------------------------------------------- - for integer HSP_CLK_PERIOD ⎞ DISP3_IF_CLK_PER_WR , ----------------------------------------------------------------- - for fractional ⎠ HSP_CLK_PERIOD Freescale Semiconductor Units ...

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... IP19 Data holdup time IP20 Control signals setup time to display interface clock 1 The exact conditions have not been finalized, but will likely match the current customer requirement for their specific display. These conditions may be device specific. Freescale Semiconductor NOTE IP20 IP18 IP17 IP19 ...

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... REV toggles every HSYNC period. Figure 49. Sharp HR-TFT Panel Interface Timing Diagram—Pixel Level 62 Horizontal timing D1 D2 IP21 1 DISPB_D3_CLK period IP23 IP22 IP24 IP25 IP26 MCIMX31/MCIMX31L Technical Data, Rev. 4.3 Table 48 lists the timing parameters. The The timing D320 Freescale Semiconductor ...

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... At a transition to an odd field (of the next frame), the negative edges of DISPB_D3_VSYNC and DISPB_D3_HSYNC coincide. — transition to an even field (of the same frame), they do not coincide. • The active intervals—during which data is transferred—are marked by the DISPB_D3_HSYNC signal being high. Freescale Semiconductor Symbol Tsplr (BGXP – Tdpcp Tclsr CLS_RISE_DELAY * Tdpcp ...

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... Odd Field Line and Field Timing - NTSC 623 624 625 1 310 311 312 313 Line and Field Timing - PAL MCIMX31/MCIMX31L Technical Data, Rev. 4 Odd Field 267 268 269 273 Even Field Odd Field 314 315 316 336 Even Field Freescale Semiconductor ...

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... Additionally, the IPU allows a programmable pause between two burst. The pause is defined in the HSP_CLK cycles. It allows to avoid timing violation between two sequential bursts or two accesses to different displays. The range of this pause is from HSP_CLK cycles. Freescale Semiconductor Electrical Characteristics Functional Description 54. These timing images correspond to active-low DISPB_D#_CS, MCIMX31/MCIMX31L Technical Data, Rev ...

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... Single access mode (all control signals are not active for one display interface clock after each display access) Figure 51. Asynchronous Parallel System 80 Interface (Type 1) Burst Mode Timing Diagram 66 Burst access mode with sampling by CS signal MCIMX31/MCIMX31L Technical Data, Rev. 4.3 Freescale Semiconductor ...

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... Single access mode (all control signals are not active for one display interface clock after each display access) Figure 52. Asynchronous Parallel System 80 Interface (Type 2) Burst Mode Timing Diagram Freescale Semiconductor Burst access mode with sampling by WR/RD signals MCIMX31/MCIMX31L Technical Data, Rev. 4.3 ...

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... Single access mode (all control signals are not active for one display interface clock after each display access) Figure 53. Asynchronous Parallel System 68k Interface (Type 1) Burst Mode Timing Diagram 68 Burst access mode with sampling by CS signal MCIMX31/MCIMX31L Technical Data, Rev. 4.3 Freescale Semiconductor ...

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... Display read operation can be performed with wait states when each read access takes up to four display interface clock cycles according to the DISP0_RD_WAIT_ST parameter in the DI_DISP0_TIME_CONF_3, DI_DISP1_TIME_CONF_3, DI_DISP2_TIME_CONF_3 Registers. Figure 55 shows timing of the parallel interface with read wait states. Freescale Semiconductor Burst access mode with sampling by ENABLE signal MCIMX31/MCIMX31L Technical Data, Rev. 4.3 Electrical Characteristics 69 ...

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... DI_DISP_SIG_POL Register). 70 WRITE OPERATION DISP0_RD_WAIT_ST=00 DISP0_RD_WAIT_ST=01 DISP0_RD_WAIT_ST=10 , Electrical Characteristics Figure 59 depict timing of asynchronous parallel interfaces based on Table 49 lists the timing parameters at display access level. All MCIMX31/MCIMX31L Technical Data, Rev. 4.3 READ OPERATION Freescale Semiconductor ...

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... DISPB_RD (READ_L) DISPB_DATA[17] (READ_H) DISPB_D#_CS DISPB_WR (WRITE_L) DISPB_DATA[16] (WRITE_H) DISPB_DATA (Input) DISPB_DATA (Output) Figure 56. Asynchronous Parallel System 80 Interface (Type 1) Timing Diagram Freescale Semiconductor IP28, IP27 IP35, IP33 IP31, IP29 read point IP37 Read Data IP39 IP46,IP44 IP47 IP45, IP43 IP42, IP41 MCIMX31/MCIMX31L Technical Data, Rev ...

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... DISPB_DATA (Output) Figure 57. Asynchronous Parallel System 80 Interface (Type 2) Timing Diagram 72 IP28, IP27 IP35, IP33 IP31, IP29 read point IP37 Read Data IP39 IP46,IP44 IP47 IP45, IP43 IP42, IP41 MCIMX31/MCIMX31L Technical Data, Rev. 4.3 IP36, IP34 IP32, IP30 IP38 IP40 Freescale Semiconductor ...

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... DISPB_PAR_RS DISPB_RD (ENABLE_L) DISPB_DATA[17] (ENABLE_H) DISPB_D#_CS DISPB_WR (READ/WRITE) DISPB_DATA (Input) DISPB_DATA (Output) Figure 58. Asynchronous Parallel System 68k Interface (Type 1) Timing Diagram Freescale Semiconductor IP28, IP27 IP35,IP33 IP31, IP29 read point IP37 Read Data IP39 IP46,IP44 IP47 IP45, IP43 IP42, IP41 MCIMX31/MCIMX31L Technical Data, Rev. 4.3 ...

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... Tdicpr–Tdicdr–1.5 Tdicpr–Tdicdr Tdcsw Tdicuw–1.5 Tdicuw MCIMX31/MCIMX31L Technical Data, Rev. 4.3 IP36, IP34 IP32, IP30 IP38 IP40 1 Typ. Max. 2 Tdicpr+1.5 3 Tdicpw+1 –Tdicur Tdicdr–Tdicur+1.5 Tdicpr–Tdicdr+Tdicur+1 –Tdicuw Tdicdw–Tdicuw+1.5 Tdicpw–Tdicdw+ Tdicuw+1.5 — — — Freescale Semiconductor Units ...

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... T HSP_CLK ceil HSP_CLK_PERIOD 10 Loopback delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a device-level output delay, board delays, a device-level input delay, an IPU input delay. This value is device specific. Freescale Semiconductor Symbol Min. Tdchw Tdicpw–Tdicdw–1.5 ...

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... Figure 60. 3-Wire Serial Interface Timing Diagram Figure 61 depicts timing of the 4-wire serial interface. For this interface, there are separate input and output data lines both inside and outside the device Functional Description Preamble MCIMX31/MCIMX31L Technical Data, Rev. 4.3 1 display IF clock cycle Input or output data Freescale Semiconductor ...

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... DISPB_SD_D (Input) Figure 61. 4-Wire Serial Interface Timing Diagram Figure 62 depicts timing of the 5-wire serial interface (Type 1). For this interface, a separate RS line is added. When a burst is transmitted within single active chip select interval, the RS can be changed at boundaries of words. Freescale Semiconductor Write Preamble Read ...

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... DISPB_SD_D_CLK DISPB_SD_D (Output) DISPB_SD_D (Input) DISPB_SER_RS Figure 62. 5-Wire Serial Interface (Type 1) Timing Diagram 78 Write 1 display IF clock cycle RW D7 Preamble Read 1 display IF clock cycle RW Preamble D7 MCIMX31/MCIMX31L Technical Data, Rev. 4.3 1 display IF clock cycle Output data 1 display IF clock cycle Input data Freescale Semiconductor ...

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... IF DISPB_SER_RS clock cycle DISPB_D#_CS DISPB_SD_D_CLK DISPB_SD_D (Output) DISPB_SD_D (Input) 1 display IF DISPB_SER_RS clock cycle Figure 63. 5-Wire Serial Interface (Type 2) Timing Diagram Freescale Semiconductor Write 1 display IF clock cycle RW D7 Preamble Read 1 display IF clock cycle RW Preamble D7 MCIMX31/MCIMX31L Technical Data, Rev. 4.3 Electrical Characteristics ...

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... MCIMX31/MCIMX31L Technical Data, Rev. 4.3 IP57, IP55 IP51, IP53 IP59 IP61 1 Typ. Max. 2 Tdicpr Tdicpr+1.5 3 Tdicpw Tdicpw+1 Tdicdr –Tdicur Tdicdr–Tdicur+1.5 Tdicpr–Tdicdr+ Tdicpr–Tdicdr+Tdicur+1.5 Tdicur 6 7 Tdicdw –Tdicuw Tdicdw–Tdicuw+1.5 Tdicpw–Tdicdw+ Tdicpw–Tdicdw+ Tdicuw Tdicuw+1.5 Tdicur — Tdicpr–Tdicdr — Freescale Semiconductor Units ...

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... HSP_CLK HSP_CLK_PERIOD 10 Loopback delay Tlbd is the cumulative propagation delay of read controls and read data. It includes an IPU output delay, a device-level output delay, board delays, a device-level input delay, an IPU input delay. This value is device specific. Freescale Semiconductor Symbol Min. Tdcsw Tdicuw–1.5 Tdchw Tdicpw– ...

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... MSHC_DATA (Intput) Figure 66. Transfer Operation Timing Diagram (Serial) 82 depict the MSHC timings, and tSCLKc tSCLKwh Figure 65. MSHC_CLK Timing Diagram tSCLKc tBSsu tDsu MCIMX31/MCIMX31L Technical Data, Rev. 4.3 Table 51 and Table 52 list the timing tSCLKwl tSCLKf tBSh tDh tDd Freescale Semiconductor ...

Page 83

... MSHC_SCLK L pulse length Setup time MSHC_BS Setup time MSHC_DATA Output delay time 1 Timing is guaranteed for NVCC from 2.7 through 3.1 V and maximum overdrive NVCC of 3.3 V. See NVCC restrictions described in Freescale Semiconductor tSCLKc tBSsu tDsu tDd NOTE Symbol Cycle tSCLKc tSCLKwh tSCLKwl ...

Page 84

... Symbol Cycle tSCLKc tSCLKwh tSCLKwl tSCLKr tSCLKf tBSsu tBSh tDsu tDh tDd 13. MCIMX31/MCIMX31L Technical Data, Rev. 4.3 1 Standards Unit Min Max 25 — — — ns — — — — — — ns — Table 53 lists the timing Freescale Semiconductor ...

Page 85

... HADDR CONTROL HWDATA HREADY HRESP A[25:0] D[15:0] WAIT REG OE/WE/IORD/IOWR CE1/CE2 RW POE Figure 68. Write Accesses Timing Diagram—PSHT=1, PSST=1 Freescale Semiconductor ADDR 1 CONTROL 1 DATA write 1 OKAY ADDR 1 DATA write 1 REG PSST MCIMX31/MCIMX31L Technical Data, Rev. 4.3 Electrical Characteristics OKAY OKAY PSHT ...

Page 86

... The output is available at the pulse-width modulator output (PWMO) external pin. 86 ADDR 1 CONTROL 1 OKAY ADDR 1 REG PSST Parameter MCIMX31/MCIMX31L Technical Data, Rev. 4.3 DATA read 1 OKAY OKAY PSHT PSL Min Max Unit 0 63 clock 1 63 clock 1 128 clock Freescale Semiconductor ...

Page 87

... Output setup time PWMO = 30 pF 4.3.19 SDHC Electrical Specifications This section describes the electrical information of the SDHC. 4.3.19.1 SDHC Timing Figure 71 depicts the timings of the SDHC, and Freescale Semiconductor Table 54 lists the PWM timing characteristics Figure 70. PWM Timing Table 54. PWM Output Timing Parameters ...

Page 88

... Figure 71. SDHC Timing Diagram Table 55. SDHC Interface Timing Parameters Symbol TLH t THL t ODL MCIMX31/MCIMX31L Technical Data, Rev. 4.3 SD4 SD3 SD2 Min Max 1 0 400 100 400 10 — 10 — — 10 — 10 –6.5 3 — 18.5 — –11.5 Freescale Semiconductor Unit kHz MHz MHz kHz ...

Page 89

... After powerup, the clock signal is enabled on SGCLK (time T0) • After 200 clock cycles, RX must be high. • The card must send a response on RX acknowledging the reset between 400 and 40000 clock cycles after T0. Freescale Semiconductor Figure 56 1/Sfreq Sfall Srise Figure 72. SIM Clock Timing Diagram ...

Page 90

... Figure 74. Active-Low-Reset Card Reset Sequence 90 response 400 clock cycles < Figure 3 T1 400 clock cycles < 400000 clock cycles < MCIMX31/MCIMX31L Technical Data, Rev. 4.3 < 200 clock cycles 1 < 40000 clock cycles 2 74): response 2 3 < 200 clock cycles 1 < 40000 clock cycles 2 3 Freescale Semiconductor ...

Page 91

... Table 57. Timing Requirements for Power Down Sequence Num Description 1 SIM reset to SIM clock stop 2 SIM reset to SIM TX data low 3 SIM reset to SIM Voltage Enable Low 4 SIM Presence Detect to SIM reset Low Freescale Semiconductor Figure 75 Srst2clk Srst2dat Srst2ven Symbol S 0.9*1/FCKIL rst2clk S 1.8*1/FCKIL ...

Page 92

... Figure 76. Test Clock Input Timing Diagram SJ4 Input Data Valid SJ6 Output Data Valid SJ7 SJ6 Output Data Valid MCIMX31/MCIMX31L Technical Data, Rev. 4.3 Figure 76 depicts the SJC test clock Figure 78 depicts the SJC test access port, SJ2 VM SJ3 VIH SJ5 Freescale Semiconductor ...

Page 93

... TCK low to output data valid SJ7 TCK low to output high impedance SJ8 TMS, TDI data set-up time SJ9 TMS, TDI data hold time SJ10 TCK low to TDO data valid Freescale Semiconductor SJ8 Input Data Valid SJ10 Output Data Valid SJ11 SJ10 Output Data Valid SJ13 Figure 79 ...

Page 94

... Data (for example, during AC97 mode of operation). 4.3.22.1 SSI Transmitter Timing with Internal Clock Figure 80 depicts the SSI transmitter timing with internal clock, and 94 Parameter MCIMX31/MCIMX31L Technical Data, Rev. 4.3 All Frequencies Unit Min Max — 100 — — ns Table 59 lists the timing parameters. Freescale Semiconductor ...

Page 95

... SS2 DAM1_T_CLK (Output) SS6 DAM1_T_FS (bl) (Output) DAM1_T_FS (wl) (Output) DAM1_TXD (Output) DAM1_RXD (Input) Note: SRXD Input in Synchronous mode only Figure 80. SSI Transmitter with Internal Clock Timing Diagram Freescale Semiconductor SS1 SS5 SS4 SS8 SS6 SS10 SS16 SS43 SS42 SS1 SS5 SS4 SS8 ...

Page 96

... Loading 96 Parameter MCIMX31/MCIMX31L Technical Data, Rev. 4.3 Min Max Unit 81.4 — ns 36.0 — ns — 36.0 — ns — — 15.0 ns — 15.0 ns — 15.0 ns — 15.0 ns — — — 15.0 ns — 15.0 ns — 15.0 ns — 10.0 — — ns — Freescale Semiconductor ...

Page 97

... SS48 AD1_RXC (Output) SS2 DAM1_T_CLK (Output) DAM1_T_FS (bl) (Output) DAM1_T_FS (wl) (Output) DAM1_RXD (Input) SS48 DAM1_R_CLK (Output) Figure 81. SSI Receiver with Internal Clock Timing Diagram Freescale Semiconductor SS1 SS5 SS4 SS9 SS11 SS20 SS51 SS47 SS50 SS1 SS5 SS4 SS9 SS7 SS11 SS20 ...

Page 98

... SS51 Oversampling clock fall time 98 Parameter MCIMX31/MCIMX31L Technical Data, Rev. 4.3 Min Max Unit 81.4 — ns 36.0 — ns — 36.0 — ns — — 15.0 ns — 15.0 ns — 15.0 ns — 15.0 ns 10.0 — — ns 15.04 — — ns — — ns — Freescale Semiconductor ...

Page 99

... SS23 DAM1_T_CLK (Input) SS27 DAM1_T_FS (bl) (Input) DAM1_T_FS (wl) (Input) DAM1_TXD (Output) DAM1_RXD (Input) Note: SRXD Input in Synchronous mode only Figure 82. SSI Transmitter with External Clock Timing Diagram Freescale Semiconductor SS22 SS25 SS26 SS29 SS31 SS37 SS44 SS22 SS26 SS25 SS29 SS31 SS37 SS44 MCIMX31/MCIMX31L Technical Data, Rev ...

Page 100

... Parameter MCIMX31/MCIMX31L Technical Data, Rev. 4.3 Min Max Unit 81.4 — ns 36.0 — ns — 6.0 ns 36.0 — ns — 6.0 ns –10.0 15.0 ns 10.0 — ns –10.0 15.0 ns 10.0 — ns — 15.0 ns — 15.0 ns — 15.0 ns 10.0 — ns 2.0 — ns — 6.0 ns Freescale Semiconductor ...

Page 101

... ID External Clock Operation SS22 (Tx/Rx) CK clock period SS23 (Tx/Rx) CK clock high period SS24 (Tx/Rx) CK clock rise time SS25 (Tx/Rx) CK clock low period SS26 (Tx/Rx) CK clock fall time Freescale Semiconductor SS22 SS26 SS25 SS30 SS32 SS35 SS40 SS22 SS26 SS25 SS30 SS32 ...

Page 102

... Parameter Table 63 lists the timing parameters MCIMX31/MCIMX31L Technical Data, Rev. 4.3 Min Max Unit –10.0 15.0 ns 10.0 — ns –10.0 15.0 ns 10.0 — ns — 6.0 ns — 6.0 ns 10.0 — ns 2.0 — ns Figure Symbol Min Max — — — Freescale Semiconductor Units ...

Page 103

... MAPBGA signal assignments), and MAPBGA ground/power ID by ball grid location for the 457 mm, 0.5 mm pitch package. 5.1.1 Production Package Outline Drawing– Figure 85. Production Package: Case 1581—0.5 mm Pitch Freescale Semiconductor MCIMX31/MCIMX31L Technical Data, Rev. 4.3 Package Information and Pinout Section 7, “Revision History,” ...

Page 104

... J14, L13, L14, L15, L16, M18, U18, V10, V11, V12, V13 QVCC1 J10, J11, K9, L11 QVCC4 N9, R9, T9, U9 SGND T14 SVCC V14 UVCC V16 UGND T16 104 Figure 69 for the 0 0 0.5 mm Ball Location MCIMX31/MCIMX31L Technical Data, Rev. 4.3 × 14 MAPBGA signal assignments. Table 65 shows the device Freescale Semiconductor ...

Page 105

... ATA_CS0 ATA_CS1 ATA_DIOR ATA_DIOW ATA_DMACK ATA_RESET BATT_LINE BCLK BOOT_MODE0 BOOT_MODE1 BOOT_MODE2 BOOT_MODE3 BOOT_MODE4 CAPTURE CAS CE_CONTROL CKIH Freescale Semiconductor Ball Location AD6 AF5 AF18 AC3 COMPARE AD3 CONTRAST AD4 AF17 AF16 AF15 AF14 AF13 AF12 AB5 AF11 AF10 AF9 AF8 AF7 ...

Page 106

... See VPG1 LBA AE22 LCS0 P26 LCS1 P21 LD0 T24 LD1 U26 LD10 V24 LD11 Y25 LD12 Y26 LD13 V21 LD14 AA25 LD15 W24 LD16 AA26 LD17 V20 LD2 T21 LD3 V25 LD4 T20 LD5 V26 LD6 U24 SCK6 T2 Freescale Semiconductor ...

Page 107

... PC_VS1 PC_VS2 PC_WAIT POR POWER_FAIL PWMO RAS READ RESET_IN RI_DCE1 RI_DTE1 RTCK RTS1 RTS2 RW RXD1 RXD2 SCK3 SCK4 SCK5 SDCKE0 SDCKE1 Freescale Semiconductor Ball Location U21 W26 SD_D_CLK Y21 AC25 AC1 See VPG0 V1 T6 SD1_CMD U3 SD1_DATA0 U1 SD1_DATA1 V2 SD1_DATA2 T7 SD1_DATA3 U2 AB25 R21 ...

Page 108

... USBOTG_DIR R1 USBOTG_NXT B3 USBOTG_STP C5 T1 A21 B19 F16 A19 WATCHDOG_RST G16 MCIMX31/MCIMX31L Technical Data, Rev. 4.3 Signal ID Ball Location TXD1 F10 TXD2 C13 A9 USB_OC C10 B10 G10 VPG0 G25 VPG1 J20 VSTBY F26 VSYNC0 N24 VSYNC3 R26 A24 WRITE R25 Freescale Semiconductor ...

Page 109

... MAPBGA ground/power ID by ball grid location for the 473 mm, 0.8 mm pitch package. 5.2.1 Production Package Outline Drawing– 0.8 mm Figure 86. Production Package: Case 1931—0.8 mm Pitch Freescale Semiconductor MCIMX31/MCIMX31L Technical Data, Rev. 4.3 Package Information and Pinout Section 7, “Revision History,” ...

Page 110

... H13, J14, L15, M15, N9, N15, P9, P15, R10, R11, R13, R14 QVCC1 J8, J9, J10, K9 QVCC4 L9, M7, M8, N8 SGND U13 SVCC U12 UVCC P18 UGND P17 110 0.8 mm shows the device connection list for signals 0.8 mm Ball Location MCIMX31/MCIMX31L Technical Data, Rev. 4.3 Table 67, which Freescale Semiconductor ...

Page 111

... A17 A18 A19 A2 A20 A21 A22 A23 A24 A25 ATA_CS0 ATA_CS1 ATA_DIOR ATA_DIOW ATA_DMACK ATA_RESET BATT_LINE BCLK Freescale Semiconductor Table 67 BGA No Connects Signal Ball Location U21 Ball Location Y6 AC5 V15 AB3 COMPARE AA3 CONTRAST Y3 Y15 Y14 V14 Y13 V13 Y12 AB5 ...

Page 112

... A15 B15 D14 C15 F13 A16 B16 A17 A13 B13 C13 A14 F12 D13 B14 C14 L2PG See VPG1 LBA V17 LCS0 M22 LCS1 N23 LD0 R23 LD1 R22 LD10 U22 LD11 R18 LD12 U20 LD13 V23 LD14 V22 Freescale Semiconductor ...

Page 113

... PC_CD1 PC_CD2 PC_POE PC_PWRON PC_READY PC_RST PC_RW PC_VS1 PC_VS2 PC_WAIT POR POWER_FAIL PWMO RAS READ RESET_IN RI_DCE1 RI_DTE1 RTCK RTS1 Freescale Semiconductor Ball Location E23 W22 W21 Y21 M23 C19 G17 B20 T20 R17 U23 SD_D_CLK U18 T17 Y2 See VPG0 T2 R4 ...

Page 114

... MCIMX31/MCIMX31L Technical Data, Rev. 4.3 Signal ID Ball Location SD5 AC16 SD6 AA15 SD7 AB15 SD8 AC15 SD9 AA14 SDBA0 AA6 SDBA1 Y7 TRSTB F15 TXD1 D9 TXD2 F11 C8 USB_OC VPG0 G21 VPG1 G22 VSTBY H18 VSYNC0 L22 VSYNC3 N20 B21 WRITE N22 Freescale Semiconductor ...

Page 115

Ball Maps GND GND SFS5 CSPI2 CSPI2_ USBOT USBOT USBOT _MISO SS2 G_DAT G_DAT G_NXT GND GND STXD4 SRXD CSPI2_ CSPI2_ USBOT USBOT 5 SS0 SPI_R G_DAT ...

Page 116

CSPI2_ USBOTG_ USBOTG USBOTG A GND GND GND SS1 DATA6 _DATA2 _DIR CSPI2_ CSPI2_ USBOTG_ USBOTG_ B GND GND STXD4 MISO SCLK DATA5 NXT CSPI2_ USBOTG_ USBOTG_ C GND GND SRXD4 SRXD5 SS0 ...

Page 117

... MCIMX31 Reference Manual (order number MCIMX31RM) MCIMX31 Chip Errata (order number MCIMX31CE) The Freescale manuals are available on the Freescale Semiconductors Web site at http://www.freescale.com/imx. These documents may be downloaded directly from the Freescale Web site, or printed versions may be ordered. ARM Ltd. documentation is available from http://www.arm.com. ...

Page 118

... Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use ...