MCIMX31VKN5 Freescale, MCIMX31VKN5 Datasheet - Page 20

• Manufacturer Part Number: MCIMX31VKN5
• Manufacturer: Freescale

Specifications of MCIMX31VKN5

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Electrical Characteristics
4.2.1.1
Silicon revision 2.0 offers two options for power-up sequencing. Option 1 is backwards compatible with
silicon revision 1.2 and earlier versions of the IC. It should be noted that using option 1 on silicon Rev. 2.0
introduces a slight increase in current drain on IOQVDD when IOQVDD is raised before NVCC21. The
expected resulting increase is in the range of 3 mA to 5 mA, which does not pose a risk to the IC.
Option 2 is an alternative power-up sequence that allows the powering up of NVCC2, NVCC21, NVCC22
with IOQVDD, NVCC1, and NVCC3-10 without producing a current drain increase on IOQVDD.
These two power-up options on the 2.0 silicon allow the user to select the optimum power-up sequence for
their application.
20
FUSE_VDD
Power-Up Sequence for Silicon Revision 2
IOQVDD, NVCC1, NVCC3–10
NVCC2, NVCC21, NVCC22
QVCC, QVCC1, QVCC4
1, 3
Hold POR Asserted
Figure 2. Power-Up Sequence for Silicon Revisions 1.2 and Previous
Release POR
1
MCIMX31/MCIMX31L Technical Data, Rev. 4.1
FVCC, MVCC,
SVCC, UVCC
1
1, 2
1
Notes:
1
2
3
1
The board design must guarantee that supplies reach 90% level before transition
to the next state, using Power Management IC or other means.
The NVCC1 supply must not precede IOQVDD by more than 0.2 V until IOQVDD
has reached 1.5 V. If IOQVDD is powered up first, there are no restrictions.
It is allowable for FVCC, MVCC, SVCC, and UVCC to be up after FUSE_VDD.
Freescale Semiconductor