SSTE32882KA1AKG IDT, Integrated Device Technology Inc, SSTE32882KA1AKG Datasheet - Page 47

• Manufacturer Part Number: SSTE32882KA1AKG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of SSTE32882KA1AKG

• Lead Free Status / RoHS Status: Compliant

CLOCK STOPPED POWER DOWN MODE
Clock Stopped Power Down Mode Entry
Clock Stopped Power Down Mode Exit
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
To support S3 Power Management mode or any other operation that allows Yn clocks to float, the SSTE32882KA1 supports a
Clock Stopped power down mode. When both inputs CK and CK are being held LOW, (V
settle at LOW because of the (10K-100K Ohm) pulldown resistor in the CK/CK input buffer, the device stops operation and
enters low-power static and standby operation. The corresponding timing are shown in “Clock Stopped Power Down Entry and
Exit with IBT On” and “Clock Stopped Power Down Entry and Exit with IBT Off“. The register device will stop its PLL and
floats all outputs except QACKE0, QACKE1, QBCKE0 and QBCKE1, which must be kept driven LOW.
The Clock Stopped power down mode can only be utilized once the DRAM received a self refresh command. In this state, the
DRAM ignores all inputs except CKE. Hence, all register outputs besides QxCKE0 and QxCKE1 can be disabled.
To enter Clock Stopped Power Down mode, the register will first enter CKE power down mode. Once in CKE power down
mode, the host will deasserts DCKEn for a minimum of one tCKoff before pulling CK and CK LOW. After holding CK and
CK LOW (V
resistor in the CK/CK input buffer, CK/CK will stay at LOW even though they are not being driven).The register is now in
Clock Stopped Power Down mode.
After CK and CK are pulled LOW, the host has to keep DCKEn stable for at least one t
point, all input receivers and input termination of the SSTE32882KA1 are disabled. The only active input circuits are CK and
CK, which are required to detect the wake up request from the host.
To wake up the register after Clock Stopped power down, the host must drive the register inputs DCS[n:0] must be driven to
HIGH (to prevent accidental access to the control registers), and DCKEn to LOW. After that, the host can apply a frequency
and phase accurate input clock signal. Within t
start becoming a function of their corresponding inputs. The state of the DCS[n:0] inputs must not be changed before the end
of t
SSTE32882KA1 can takes place.
STAB
. The input clock CK and CK must be stable for a time equal or greater than t
IL(static)
THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
) for at least one tCKEV, both CK and CK can be floated (because of the (10K-100K Ohm) pulldown
ACT
after CK and CK resumed normal operation, the SSTE32882KA1 outputs
47
CKEV
STAB
IL(static)
COMMERCIAL TEMPERATURE RANGE
before any access to the
before it can float DCKEn. At this
SSTE32882KA1
) or float (will eventually
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