ADSP-BF592KCPZ Analog Devices Inc, ADSP-BF592KCPZ Datasheet
ADSP-BF592KCPZ
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ADSP-BF592KCPZ Summary of contents
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... DMA ACCESS BUS DCB DEB BOOT ROM Figure 1. Processor Block Diagram One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 Blackfin Embedded Processor ADSP-BF592 2 S channels SPORT1 PORT F PPI TIMER2–0 GPIO UART SPI0 SPORT0 PORT G SPI1 TWI www ...
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... ADSP-BF592 TABLE OF CONTENTS Features ................................................................. 1 Memory ................................................................ 1 Peripherals ............................................................. 1 Revision History ...................................................... 2 General Description ................................................. 3 Portable Low-Power Architecture ............................. 3 System Integration ................................................ 3 Processor Peripherals ............................................. 3 Blackfin Processor Core .......................................... 3 Memory Architecture ............................................ 5 DMA Controllers .................................................. 8 Watchdog Timer .................................................. 8 Timers ............................................................... 8 Serial Ports .......................................................... 8 Serial Peripheral Interface (SPI) Ports ........................ 9 UART Port .......................................................... 9 Parallel Peripheral Interface (PPI) ............................. 9 TWI Controller Interface ...................................... 10 Ports ...
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... UART parallel peripheral interface (PPI); and a two-wire interface (TWI) controller. ADSP-BF592 PROCESSOR PERIPHERALS 3 The ADSP-BF592 processor contains a rich set of peripherals 2 connected to the core via several high-bandwidth buses, provid- 2 ing flexibility in system configuration as well as excellent overall system performance (see ...
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... ADSP-BF592 DA1 32 DA0 32 32 RAB SD 32 LD1 32 LD0 32 R7.H R7.L R6.H R6.L R5.H R5.L R4.H R4.L R3.H R3.L R2.H R2.L R1.H R1.L R0.H R0.L 32 population count, modulo 2 multiply, divide primitives, satu- ration and rounding, and sign/exponent detection. The set of video instructions include byte alignment and packing opera- ...
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... See the VisualDSP++ documentation for more information. Custom ROM (Optional) The on chip L1 Instruction ROM on the ADSP-BF592 may be customized to contain user code with the following features: • 64K bytes of L1 Instruction ROM available for custom code • Ability to restrict access to all or specific segments of the on ...
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... ADSP-BF592 • Nonmaskable Interrupt (NMI) – The NMI event can be generated by the software watchdog timer or by the NMI input signal to the processor. The NMI event is frequently used as a power-down indicator to initiate an orderly shut- down of the system. • Exceptions – Events that occur synchronously to program flow (in other words, the exception is taken before the instruction is allowed to complete) ...
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... IVG10 IVG10 IVG10 IVG10 IVG11 IVG11 IVG11 IVG11 IVG11 IVG12 IVG12 IVG12 – – – – IVG13 IVG13 IVG13 Rev. PrC | Page August 2010 ADSP-BF592 Default Core SIC Interrupt Interrupt ID Assignment 0 0 IAR0 1 0 IAR0 2 0 IAR0 3 0 IAR0 4 0 IAR0 ...
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... ADSP-BF592 DMA CONTROLLERS The processor has multiple, independent DMA channels that support automated data transfers with minimal overhead for the processor core. DMA transfers can occur between the pro- cessor’s internal memories and any of its DMA-capable peripherals. DMA-capable peripherals include the SPORTs, SPI ports, UART, and PPI ...
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... PPI_CONTROL register. Frame Capture Mode Frame capture mode allows the video source(s) to act as a slave (for frame capture for example). The ADSP-BF592 processor controls when to read from the video source(s). PPI_FS1 is an HSYNC output and PPI_FS2 is a VSYNC output. Output Mode Output mode is used for transmitting video or other data with up to three output frame syncs ...
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... ADSP-BF592 video (EAV) and start of active video (SAV) preamble symbols, or any data present during the vertical blanking intervals. In this mode, the control byte sequences are not stored to memory; they are filtered by the PPI. After synchronizing to the start of Field 1, the PPI ignores incoming samples until it sees an SAV code ...
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... Hibernate Disabled — Disabled Disabled Off For more information about PLL controls, see the “Dynamic Power Management” chapter in the ADSP-BF59x Blackfin Pro- cessor Hardware Reference. Sleep Operating Mode—High Dynamic Power Savings The sleep mode reduces dynamic power dissipation by disabling the clock to the processor core (CCLK) ...
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... Using Third Overtone Crystals with the ADSP-218x DSP on the Analog Devices website (www.analog.com)—use site search on “EE-168.” The Blackfin core runs at a different clock rate than the on-chip peripherals ...
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... PF8/SPI0_SSEL2 to select a single SPI EEPROM/flash device, submits a read command and suc- cessive address bytes (0×00) until a valid 8-, 16-, 24-, or 32- Rev. PrC | Page August 2010 ADSP-BF592 Idle/No Boot Reserved SPI1 master boot from Flash, using SPI1_SSEL5 on PG11 SPI1 slave boot from external master ...
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... Blackfin processors also fully emulates the ADSP-BF592 processor. EZ-KIT Lite® Evaluation Board For evaluation of the ADSP-BF592 processor, use the EZ-KIT Lite boards soon to be available from Analog Devices. When these evaluation kits are available, order using part number ADZS-BF592-EZLITE ...
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... This document is updated regularly to keep pace with improvements to emulator support. RELATED DOCUMENTS The following publications that describe the ADSP-BF592 pro- cessor (and related processors) can be ordered from any Analog Devices sales office or accessed electronically on our website: • ...
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... ADSP-BF592 SIGNAL DESCRIPTIONS Signal definitions for the ADSP-BF592 processor are listed in Table 9. In order to maintain maximum function and reduce package size and pin count, some pins have dual, multiplexed functions. In cases where pin function is reconfigurable, the default state is shown in plain text, while the alternate function is shown in italics ...
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... ALL SUPPLIES MUST BE POWERED See Operating Conditions on Page P I/O Power Supply P Internal Power Supply G Ground for All Supplies (Back Side of LFCSP Package.) Rev. PrC | Page August 2010 ADSP-BF592 2 C specification for the proper resistor 2 C specification for the proper resistor 18. Driver Type A A ...
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... Must remain powered (even if the associated function is not used). 2 Bidirectional leads (PF15–0, PG15–0) and input leads (TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE2–0) of the ADSP-BF592 processor are 3.3 V tolerant (always accept up to 3.6 V maximum V ). Voltage compliance (on outputs, V ...
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... Preliminary Technical Data ADSP-BF592 Clock Related Operating Conditions Table 10 describes the core clock timing requirements for the ADSP-BF592 processor. Take care in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the maximum core clock and system clock (see Table 12). Table 11 describes phase-locked loop operating conditions ...
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... Applies to bidirectional pins SCL and SDA. 5 Applies to all signal pins. 6 Guaranteed, but not tested. 7 See the ADSP-BF52x Blackfin Processor Hardware Reference Manual for definition of sleep, deep sleep, and hibernate operating modes. 8 See Table 13 for the list of I power vectors covered. DDINT ...
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... All specifications and references to ADSP-BF592 Blackfin processor are preliminary and subject to change. 2 The values are not guaranteed as stand-alone maximum specifications. They must be combined with static current per the equations of 3 Valid frequency and voltage ranges are model-specific. See ...
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... DDEXT ESD SENSITIVITY Table 17. is outside speci- DDEXT 1 3 PACKAGE INFORMATION The information presented in details about the package branding for the ADSP-BF592 proces- sor. For a complete listing of product availability, see Guide on Page /I ) cur 18. Note that the V OH table. Rev. PrC | Page August 2010 ...
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... If the DF bit in the PLL_CTL register is set, the minimum f 5 Applies after power-up sequence is complete. See Table 10 to Min 5 11 × t VCO specification is 24 MHz. CKIN Table 21 and Figure 8 for power-up reset timing. Rev. PrC | Page August 2010 ADSP-BF592 V V DDEXT DDEXT 1.8 V Nominal 2.5/3.3 V Nominal Max Min × ...
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... ADSP-BF592 t CKIN CLKIN t CKINL CLKBUF Table 21. Power-Up Reset Timing Parameter Timing Requirements t RESET Deasserted after the V RST_IN_PWR Specification CLKIN V DD_SUPPLIES t CKINH t WRST Figure 7. Clock and Reset Timing , V , and CLKIN Pins are Stable and Within DDINT DDEXT t RST_IN_PWR Figure 8. Power-Up Reset Timing Rev ...
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... TBD TBD DATA SAMPLED / FRAME SYNC SAMPLED t PCLKW t HFSPE t t SDRPE HDRPE Figure 9. PPI GP Rx Mode with External Frame Sync Timing Rev. PrC | Page August 2010 ADSP-BF592 V V DDEXT DDEXT 2.5/3.3V Nominal Max Min Max TBD TBD TBD TBD TBD TBD ...
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... ADSP-BF592 PPI_CLK PPI_FS1/2 PPI_DATA FRAME SYNC DRIVEN PPI_CLK t DFSPE t HOFSPE PPI_FS1/2 t SDRPE PPI_DATA FRAME SYNC DRIVEN PPI_CLK t DFSPE t HOFSPE PPI_FS1/2 PPI_DATA DATA DRIVEN / FRAME SYNC SAMPLED SFSPE HFSPE PCLKW t DDTPE t HDTPE Figure 10. PPI GP Tx Mode with External Frame Sync Timing DATA ...
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... RSCLKE 3 TBD TBD 1.8V Nominal Min 1 TBD 1 TBD 1 TBD 1 TBD TBD TBD 2 TBD TBD Rev. PrC | Page August 2010 ADSP-BF592 V V DDEXT DDEXT 2.5/3.3V Nominal Max Min Max 3.6 5.4 2 × t SCLK 4 × t TSCLKE 4 × t RSCLKE TBD 12 0 TBD ...
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... ADSP-BF592 DATA RECEIVE—INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE t SCLKIW RSCLKx t DFSI t HOFSI RFSx (OUTPUT) t SFSI RFSx (INPUT) t SDRI DRx DATA TRANSMIT—INTERNAL CLOCK DRIVE EDGE SAMPLE EDGE t SCLKIW TSCLKx t D FSI t HOFSI TFSx (OUTPUT) t SFSI TFSx (INPUT) t DDTI t HDTI DTx Table 25. Serial Ports— ...
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... DDTLFSE t DTENLFSE 1ST BIT DRIVE SAMPLE DRIVE EDGE EDGE EDGE t DDTLFSE 1ST BIT Figure 15. Serial Ports — External Late Frame Sync Rev. PrC | Page August 2010 ADSP-BF592 V V DDEXT DDEXT 2.5/3.3V Nominal Max Min TBD 0 and t apply. DDTLFSE DTENLFSE Max Unit ...
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... ADSP-BF592 TSCLKx (INPUT) TFSx (INPUT) RSCLKx (INPUT) RFSx (INPUT) Table 27. Serial Ports—Gated Clock Mode Parameter Timing Requirements t Receive Data Setup Before TSCLKx SDRI t Receive Hold After TSCLKx HDRI Switching Characteristics t Transmit Data Delay After TSCLKx DDTI t Transmit Data Hold After TSCLKx ...
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... Preliminary Technical Data GATED CLOCK MODE DATA RECEIVE TSCLKx (OUT) t SDRI DRx DELAY TIME DATA TRANSMIT TFS/TMR (OUT) t DFTSCLKCNV TSCLKx (OUT) t DFTSCLKCNV TSCLKx (OUT) t DDTI t HDTI DTx Figure 17. Serial Port Gated Clock Mode Rev. PrC | Page August 2010 ADSP-BF592 t HDRI t DCNVLTSCLK t DCNVLTSCLK ...
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... ADSP-BF592 Serial Peripheral Interface (SPI) Port—Master Timing Table 28 and Figure 18 describe SPI port master operations. Table 28. Serial Peripheral Interface (SPI) Port—Master Timing Parameter Timing Requirements t Data Input Valid to SCK Edge (Data Input Setup) SSPIDM t SCK Sampling Edge to Data Input Invalid ...
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... SPICLS SPICHS t DDSPID t HDSPID t HSPID t t HDSPID DDSPID t SSPID Figure 19. Serial Peripheral Interface (SPI) Port—Slave Timing Rev. PrC | Page August 2010 ADSP-BF592 V V DDEXT DDEXT 1.8V Nominal 2.5/3.3V Nominal Max Min 2 × t – 1.5 SCLK 2 × t – 1.5 SCLK 4 × t SCLK 2 × ...
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... ADSP-BF592 Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing The UART ports receive and transmit operations are described in the ADSP-BF59x Hardware Reference Manual. General-Purpose Port Timing Table 30 and Figure 20 describe general-purpose port operations. Table 30. General-Purpose Port Timing Parameter Timing Requirement ...
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... TBD 1 TBD 1 2 TBD 2 TBD TBD t TOD t t TIS TIH Figure 21. Timer Cycle Timing Min Figure 22. Timer Clock Timing Rev. PrC | Page August 2010 ADSP-BF592 V V DDEXT DDEXT 1.8V Nominal 2.5/3.3V Nominal Max Min SCLK SCLK 8 –2 32 TBD t – 1.5 (2 SCLK ...
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... ADSP-BF592 JTAG Test And Emulation Port Timing Table 33 and Figure 23 describe JTAG port operations. Table 33. JTAG Port Timing Parameter Timing Requirements t TCK Period TCK t TDI, TMS Setup Before TCK High STAP t TDI, TMS Hold After TCK High HTAP t System Inputs Setup Before TCK High ...
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... OUTPUT DRIVE CURRENTS Figure 30 through Figure 29 show typical current-voltage char- acteristics for the output drivers of the ADSP-BF592 processor. The curves represent the current drive capability of the output drivers. See Table 9 on Page 16 for information about which driver type corresponds to a particular pin. ...
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... ADSP-BF592 –10 –20 –30 –40 –50 0 0.5 1.0 SOURCE VOLTAGE (V) Figure 29. Driver Type B Current (1.8V V 150 120 – 30 – 60 – 90 – 120 – 150 0 0.5 1.0 1.5 2.0 SOURCE VOLTAGE (V) Figure 30. Driver Type C Current (3.3V V 100 – 25 – 50 – 75 – 100 0 0 ...
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... The graphs in these figures may not be linear outside the ranges shown the total leak Figure 36. Driver Type A Typical Rise and Fall Times (10%–90%) vs. Rev. PrC | Page August 2010 ADSP-BF592 Figure ) /2. DDEXT TESTER PIN ELECTRONICS 50: T1 45: 70 50: (impedance) 50 4.04 r 1.18 ns 0.5pF 2pF 400: Figure 35 ...
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... ADSP-BF592 100 LOAD CAPACITANCE (pF) Figure 37. Driver Type A Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (2. 100 LOAD CAPACITANCE (pF) Figure 38. Driver Type A Typical Rise and Fall Times (10%–90%) vs. Load Capacitance (3. 100 LOAD CAPACITANCE (pF) Figure 39. Driver Type C Typical Rise and Fall Times (10%–90%) vs. ...
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... MIL-STD-883 (Method 1012.1). All measurements use a 2S2P JEDEC test board Typical Unit 23.5 °C/W 20.9 °C/W 20.2 °C/W 11.2 °C/W 9.5 °C/W 0.21 °C/W 0.36 °C/W 0.43 °C/W can be used for a first ) P D Rev. PrC | Page August 2010 ADSP-BF592 ...
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... ADSP-BF592 64-LEAD LFCSP PIN ASSIGNMENT Table 35 lists the LFCSP pins by signal mnemonic. the LFCSP by pin number. Table 35. 64-Lead LFCSP Pin Assignment (Alphabetically by Signal) Signal Pin No. Signal BMODE0 29 PF7 BMODE1 28 PF8 BMODE2 27 PF9 CLKBUF/SCLK 57 PF10 CLKIN 61 PF11 EMU 19 PF12 EXT_WAKE 51 PF13 GND ...
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... LFCSP TOP VIEW PIN 16 PIN 17 PIN 32 Figure 42. 64-Lead LFCSP Lead Configuration (Top View) PIN 49 PIN 64 PIN 48 GND PAD (PIN 65) PIN 33 PIN 32 PIN 17 Figure 43. 64-Lead LFCSP Lead Configuration (Bottom View) Rev. PrC | Page August 2010 ADSP-BF592 PIN 48 PIN 33 PIN 1 PIN 1 INDICATOR PIN 16 ...
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... Table 37. Surface Mount Design Supplement Package 64-Lead LFCSP PLANNED MODELS The products listed in the table below are planned for production. Model 2, 3 ADSP-BF592KCPZ 2, 3 ADSP-BF592BCPZ 1 Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see specification which is the only temperature specification RoHS Compliant part. ...
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... Preliminary Technical Data ORDERING GUIDE The products listed in the table below are planned for sampling. Model 2, 3 ADSP-BF592KCPZ-X 1 Referenced temperature is ambient temperature. The ambient temperature is not a specification. Please see specification which is the only temperature specification RoHS Compliant part. 3 Available with a wide variety of audio algorithm combinations sold as part of a chipset and bundled with necessary software. For a complete list, visit our website at www ...
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... ADSP-BF592 ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Rev. PrC | Page August 2010 Preliminary Technical Data ...